LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1091

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 1024.Structure of a message object in the message RAM
<Document ID>
User manual
UMASK
IF1/2_MCTRL
RMTEN
IF1/2_MCTRL
DATA0
IF1/2_DA1
42.10.6.2.1 Message objects
42.10.6.2.2 CAN message interface command request registers
TXRQST
DATA1
MSK[28:0]
Table 1023.Message interface registers
There are 32 Message Objects in the Message RAM. To avoid conflicts between CPU
access to the Message RAM and CAN message reception and transmission, the CPU
cannot directly access the Message Objects. The message objects are accessed through
the IFx Interface Registers.
A message object contains the information from the various bits in the message interface
registers.
message object. The bits of a message object and the respective interface register where
this bit is set or cleared are shown. For bit functions see the corresponding interface
register.
A message transfer is started as soon as the CPU has written the message number to the
Command Request Register. With this write operation the BUSY bit is automatically set to
‘1’ and the signal CAN_WAIT_B is pulled LOW) to notify the CPU that a transfer is in
progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the Interface
Register and the Message RAM has completed. The BUSY bit is set back to zero and the
signal CAN_WAIT_B is set back).
IF1 register names
IF1_CMDREQ
IF1_CMDMASK
IF1_MASK1
IF1_MASK2
IF1_ARB1
IF1_ARB2
IF1_MCTRL
IF1_DA1
IF1_DA2
CIF1_DB1
IF1_DB2
MSGVAL
IF1/2_MSK1/2
DATA2
MXTD
IF1/2_DA2
Table 1024
ID[28:0]
MDIR
All information provided in this document is subject to legal disclaimers.
DATA3
IF1/2_ARB1/2
below shows a schematic representation of the structure of the
IF1 register set
IF1 command request
IF1 command mask
IF1 mask 1
IF1 mask 2
IF1 arbitration 1
IF1 arbitration 2
IF1 message control
IF1 data A1
IF1 data A2
IF1 data B1
IF1 data B2
Rev. 00.13 — 20 July 2011
XTD
EOB
DATA4
DIR
IF1/2_DB1
NEWDAT
DATA5
DLC3
IF2 register names
IF2_CMDREQ
IF2_CMDMASK
IF2_MSK1
IF2_MSK2
IF2_ARB1
IF2_ARB2
IF2_MCTRL
IF2_DA1
IF2_DA2
IF2_DB1
IF2_DB2
MSGLST
IF1/2_MCTRL
DATA6
DLC2
RXIE
IF1/2_MCTRL
DATA7
IF1/2_DB2
Chapter 42: Appendix
IF2 register set
IF2 command request
IF2 command mask
IF2 mask 1
IF2 mask 2
IF2 arbitration 1
IF2 arbitration 2
IF2 message control
IF2 data A1
IF2 data A2
IF2 data B1
IF2 data B2
DLC1
UM10430
TXIE
© NXP B.V. 2011. All rights reserved.
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INTPND
DLC0