LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 995

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.4.7.1 32 kHz oscillator
42.4.7.2 IRC
42.4.7.3 Crystal oscillator
42.4.7 Functional description
Table 945. Output stage 20 control register (OUTCLK_20_CTRL, addresses 0x4005 0098) bit
The 32 kHz oscillator output is controlled by the CREG block (see
and the Alarm timer are connected directly to the 32 kHz oscillator.
The IRC is a trimmed 12 MHz internal oscillator. Although it's part of the CGU, the CGU
has no control over this clock source. The IRC is put into power down depending on the
power saving mode.
The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see
Table
The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL.
The oscillator can operate in one of two modes: slave mode and oscillation mode.
Bit
27:24
31:28
•
In slave mode the input clock signal should be coupled by means of a capacitor of 100
pF (C
XTAL2 pin in this configuration can be left unconnected.
932).
Symbol
CLK_SEL
-
C
description
in
Figure
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153, drawing a), with an amplitude of at least 200 mVrms. The
Rev. 00.13 — 20 July 2011
…continued
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Description
Clock-source selection.
32 kHz oscillator
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
Reserved
Crystal oscillator
PLL0
PLL1
Reserved
Reserved
IDIVA
IDIVB
IDIVC
IDIVD
IDIVE
Reserved
IRC (default)
Chapter 42: Appendix
Table
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x01
-
31). The RTC
995 of 1164
Access
R/W
-