LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 597

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.6 SCT start condition register
24.6.7 SCT counter register
Table 504. SCT stop condition register (STOP - address 0x4000 0010) bit description
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
START_L (address 0x4000 4014) and START_H (address 0x4000 4016). Both the L and
H registers can be read or written in a single 32-bit read or write operation, or they can be
read or written individually.
The bits in this register select which event(s), if any, clear the STOP bit in the Control
register. (Since no events can occur when HALT is 1, HALT can only be cleared by
software writing the Control register.)
Table 505. SCT start condition register (START - address 0x4000 0014) bit description
If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the
_L and _H bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
COUNT_L (address 0x4000 4040) and COUNT_H (address 0x4000 4042). Both the L
and H registers can be read or written in a single 32-bit read or write operation, or they
can be read or written individually. In this case, the L and H registers count independently
under the control of the other registers.
Attempting to write a counter while it is running will not affect the counter but will produce
a bus error. Software can read the counter register(s) at any time.
Table 506. SCT counter register (COUNT - address 0x4000 0040) bit description
Bit
15:0
31:16 STOPMSK_H
Bit
15:0
31:16 STARTMSK_H
Bit
15:0
31:16
Symbol
STOPMSK_L
Symbol
STARTMSK_L
Symbol
CTR_L
CTR_H
All information provided in this document is subject to legal disclaimers.
Description
When UNIFY = 0, read or write the 16-bit L counter value. When
UNIFY = 1, read or write the lower 16 bits of the 32-bit unified
counter.
When UNIFY = 0, read or write the 16-bit H counter value. When
UNIFY = 1, read or write the upper 16 bits of the 32-bit unified
counter.
Rev. 00.13 — 20 July 2011
Description
If bit n is one, event n sets the STOP_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
If bit n is one, event n sets the STOP_H bit in the CTRL register
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
Description
If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
597 of 1164
Reset
value
0
0
Reset
value
0
0
Reset
value
0
0