LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1122

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
43.3 Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Boot process timing parameters . . . . . . . . . . . .31
Table 11. Security API calls . . . . . . . . . . . . . . . . . . . . . . .34
Table 12. NVIC pin description . . . . . . . . . . . . . . . . . . . . .36
Table 13. Connection of interrupt sources to the NVIC . .37
Table 14. Register overview: NVIC (base address 0xE000
Table 15. Event router clocking and power control. . . . . .40
Table 16. Event router inputs . . . . . . . . . . . . . . . . . . . . . .41
Table 17. Event router pin description . . . . . . . . . . . . . . .41
Table 18. Register overview: Event router (base address
Table 19. Level configuration register (HILO - address
Table 20. EDGE and HILO combined register settings . .44
Table 21. Edge configuration register (EDGE - address
Table 22. Interrupt clear enable register (CLR_EN - address
Table 23. Event set enable register (SET_EN - address
Table 24. Interrupt status register (STATUS - address
Table 25. Event enable register (ENABLE - address 0x4004
Table 26. Interrupt clear status register (CLR_STAT -
Table 27. Interrupt set status register (SET_STAT - address
Table 28. CREG clocking and power control . . . . . . . . . .54
Table 29. Register overview: Configuration registers (base
Table 30. IRC trim register (IRCTRM, address 0x4004
Table 31. CREG0 register (CREG0, address 0x4004 3004)
Table 32. Power mode control register (PMUCON, address
Table 33. Memory mapping register (M3MEMMAP, address
Table 34. CREG5 control register (CREG5, address 0x4004
Table 35. DMA muxing register (DMAMUX, address 0x4004
Table 36. ETB SRAM configuration register (ETBCFG,
<Document ID>
User manual
Ordering information . . . . . . . . . . . . . . . . . . . . .7
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .7
Ordering information (parts with on-chip flash). .8
Ordering options (parts with on-chip flash) . . . . .8
LPC185x/3x/2x/1x SRAM configuration . . . . . .15
LPC185x/3x/2x/1x Flash configuration . . . . . . .15
Boot mode when OTP BOOT_SRC bits are
programmed . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Boot mode when OPT BOOT_SRC bits are zero.
23
Image header . . . . . . . . . . . . . . . . . . . . . . . . . .26
E000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
0x4004 4000) . . . . . . . . . . . . . . . . . . . . . . . . . .42
0x4004 4000) bit description
0x4004 4004) bit description
0x4004 4FD8) bit description . . . . . . . . . . . . . .47
0x4004 4FDC) bit description . . . . . . . . . . . . . .48
0x4004 4FE0) bit description . . . . . . . . . . . . . .49
4FE4) bit description. . . . . . . . . . . . . . . . . . . . .50
address 0x4004 4FE8) bit description . . . . . . .51
0x4004 4FEC) bit description . . . . . . . . . . . . . .52
address 0x4004 3000) . . . . . . . . . . . . . . . . . . .55
3000) bit description . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
0x4004 3008) bit description
0x4004 3100) bit description
3118) bit description . . . . . . . . . . . . . . . . . . . .57
311C) bit description . . . . . . . . . . . . . . . . . . . .57
address 0x4004 3128) bit description . . . . . . .60
. . . . . . . . . . . . .42
. . . . . . . . . . . . .45
. . . . . . . . . . . . .57
. . . . . . . . . . . . .57
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 37. CREG6 control register (CREG6, address 0x4004
Table 38. Part ID register (CHIPID, address 0x4004 3200)
Table 39. Register overview: Power Mode Controller (PMC)
Table 40. Hardware sleep event enable register
Table 41. Sleep power mode register
Table 42. Typical settings for PMC power modes . . . . . . 65
Table 43. CGU clocking and power control . . . . . . . . . . . 66
Table 44. CGU0 base clocks . . . . . . . . . . . . . . . . . . . . . 68
Table 45. Available clock sources for clock generators with
Table 46. Clock sources for output stages. . . . . . . . . . . . 69
Table 47. CGU pin description. . . . . . . . . . . . . . . . . . . . . 71
Table 48. Register overview: CGU (base address 0x4005
Table 49. FREQ_MON register (FREQ_MON, address
Table 50. XTAL_OSC_CTRL register (XTAL_OSC_CTRL,
Table 51. PLL0USB status register (PLL0USB_STAT,
Table 52. PLL0USB control register (PLL0USB_CTRL,
Table 53. PLL0USB M-divider register (PLL0USB_MDIV,
Table 54. PLL0USB NP-divider register
Table 55. PLL0AUDIO status register (PLL0AUDIO_STAT,
Table 56. PLL0AUDIO control register (PLL0AUDIO_CTRL,
Table 57. PLL0AUDIO M-divider register
Table 58. PLL0 AUDIO NP-divider register
Table 59. PLL0AUDIO fractional divider register
Table 60. PLL1 status register (PLL1_STAT, address
312C) bit description . . . . . . . . . . . . . . . . . . . 60
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61
(base address 0x4004 2000) . . . . . . . . . . . . . . 64
(PD0_SLEEP0_HW_ENA - address
0x4004 2000) bit description . . . . . . . . . . . . . . 64
(PD0_SLEEP0_MODE - address 0x4004 201C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64
selectable inputs
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
0x4005 0014) bit description
address 0x4005 0018) bit description . . . . . . . 74
address 0x4005 001C) bit description . . . . . . 75
address 0x4005 0020) bit description
address 0x4005 0024) bit description
(PLL0USB_NP_DIV, address 0x4005 0028) bit
description
address 0x4005 002C) bit description . . . . . . 77
address 0x4005 0030) bit description
(PLL0AUDIO_MDIV, address 0x4005 0034) bit
description
(PLL0AUDIO_NP_DIV, address 0x4005 0038) bit
description
(PLL0AUDIO_FRAC, address 0x4005 003C) bit
description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 43: Supplementary information
. . . . . . . . . . . . . . . . . . . . . . 69
UM10430
© NXP B.V. 2011. All rights reserved.
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