LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 690

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
29.4.4 Interrupt set enable register
29.4.5 Interrupt status register
29.4.6 Interrupt enable register
29.4.7 Clear status register
29.4.8 Set status register
Table 616. Interrupt set enable register (SET_EN - 0x4004 0FDC) bit description
Table 617. Interrupt status register (STATUS - 0x4004 0FE0) bit description
Table 618. Interrupt enable register (ENABLE - 0x4004 0FE4) bit description
Table 619. Interrupt clear status register (CLR_STAT - 0x4004 0FE8) bit description
Table 620. Interrupt set status register (SET_STAT - 0x4004 0FEC) bit description
Bit
0
31:1
Bit
0
31:1
Bit
0
31:1
Bit
0
31:1
Bit
0
31:1
Symbol
SET_EN
-
Symbol
STAT
-
Symbol
EN
-
Symbol
CSTAT
-
Symbol
SSTAT
-
All information provided in this document is subject to legal disclaimers.
Description
Writing a 1 to this bit sets the interrupt enable bit in the
ENABLE register.
Reserved.
Description
A 1 in this bit shows that the STATUS interrupt has been
raised.
Reserved.
Description
A 1 in this bit shows that the STATUS interrupt has been
enabled and that the STATUS interrupt request signal is
asserted when STAT = 1 in the STATUS register.
Reserved.
Description
Writing a 1 to this bit clears the STATUS interrupt bit in the
STATUS register.
Reserved.
Description
Writing a 1 to this bit sets the STATUS interrupt bit in the
STATUS register.
Reserved.
Rev. 00.13 — 20 July 2011
Chapter 29: LPC18xx Alarm timer
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
-
Reset value
0
-
Reset value
0
-
Reset value
0
-
Reset value
0
-
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