LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 413

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.2 Port state and control
It is also not necessary to initially prime Endpoint 0 because the first packet received will
always be a setup packet. The contents of the first setup packet will require a response in
accordance with USB device framework command set (see USB Specification Rev. 2.0,
chapter 9).
From a chip or system reset, the device controller enters the powered state. A transition
from the powered state to the attach state occurs when the Run/Stop bit is set to a ‘1’.
After receiving a reset on the bus, the port will enter the defaultFS or defaultHS state in
accordance with the reset protocol described in Appendix C.2 of the USB Specification
Rev. 2.0. The following state diagram depicts the state of a USB 2.0 device.
Remark: Endpoint 0 is designed as a control endpoint only and does not need to be
configured using ENDPTCTRL0 register.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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