LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1130

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 392. USB Mode register in host mode (USBMODE_H
Table 393. USB Endpoint Setup Status register
Table 394. USB Endpoint Prime register (ENDPTPRIME -
Table 395. USB Endpoint Flush register (ENDPTFLUSH -
Table 396. USB Endpoint Status register (ENDPTSTAT -
Table 397. USB Endpoint Complete register
Table 398. USB Endpoint 0 Control register (ENDPTCTRL0
Table 399. USB Endpoint 1 to 3 control registers
Table 400. Ethernet clocking and power control . . . . . . .478
Table 401. Ethernet pin description . . . . . . . . . . . . . . . . .479
Table 402. Register overview: Ethernet MAC and DMA (base
Table 403. MAC Configuration register (MAC_CONFIG,
Table 404. MAC Frame filter register
Table 405. MAC Hash table high register
Table 406. MAC Hash table low register
Table 407. MAC MII Address register (MAC_MII_ADDR,
Table 408. CSR clock range values. . . . . . . . . . . . . . . . .487
Table 409. MII Data register (MAC_MII_DATA, address
Table 410. MAC Flow control register (MAC_FLOW_CTRL,
Table 411. MAC VLAN tag register (MAC_VLAN_TAG,
Table 412. MAC Debug register (MAC_DEBUG, address
Table 413. MAC Remote wake-up frame filter register
Table 414. MAC PMT control and status register
Table 415. MAC Interrupt status register (MAC_INTR,
Table 416. MAC Interrupt mask register (MAC_INTR_MASK,
Table 417. MAC Address 0 high register
<Document ID>
User manual
description . . . . . . . . . . . . . . . . . . . . . . . . . .469
- address 0x4000 71A8) bit description . . . .470
(ENDPTSETUPSTAT - address 0x4000 71AC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .471
address 0x4000 71B0) bit description . . . . .472
address 0x4000 71B4) bit description . . . . . .472
address 0x4000 71B8) bit description . . . . . .473
(ENDPTCOMPLETE - address 0x4000 71BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .474
- address 0x4000 71C0) bit description . . . .474
(ENDPTCTRL - address 0x4000 71C4
(ENDPTCTRL1) to 0x4000 71CC
(ENDPTCTRL3)) bit description . . . . . . . . . .475
address 0x4001 0000) . . . . . . . . . . . . . . . . . .480
address 0x4001 0000) bit description . . . . . .481
(MAC_FRAME_FILTER, address 0x4001 0004)
bit description . . . . . . . . . . . . . . . . . . . . . . . .484
(MAC_HASHTABLE_HIGH, address 0x4001
0008) bit description . . . . . . . . . . . . . . . . . . .486
(MAC_HASHTABLE_LOW, address 0x4001
0008) bit description . . . . . . . . . . . . . . . . . . .486
address 0x4001 0010) bit description . . . . . .487
0x4001 0014) bit description
address 0x4001 0018) bit description . . . . . .489
address 0x4001 01C) bit description . . . . . .490
0x4001 0024) bit description
(MAC_RWAKE_FRFLT, address 0x4001 0028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .492
(MAC_PMT_CTRL_STAT, address 0x4001 002C)
bit description . . . . . . . . . . . . . . . . . . . . . . . .492
address 0x4001 0038) bit description . . . . . .493
address 0x4001 003C) bit description . . . . .493
. . . . . . . . . . . .488
. . . . . . . . . . . .490
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 418. MAC Address 0 low register
Table 419. MAC IEEE1588 time stamp control register
Table 420. Time stamp snapshot dependency on register bits
Table 421. DMA Bus mode register (DMA_BUS_MODE,
Table 422. Programmable burst length settings . . . . . . 498
Table 423. DMA Transmit poll demand register
Table 424. DMA Receive poll demand register
Table 425. DMA Receive descriptor list address register
Table 426. DMA Transmit descriptor list address register
Table 427. DMA Status register (DMA_STAT, address
Table 428. DMA operation mode register (DMA_OP_MODE,
Table 429. DMA Interrupt enable register (DMA_INT_EN,
Table 430. DMA Missed frame and buffer overflow counter
Table 431. DMA Receive interrupt watchdog timer register
Table 432. DMA Current host transmit descriptor register
Table 433. DMA Current host receive descriptor register
Table 434. DMA Current host transmit buffer address
Table 435. DMA Current host receive buffer address register
Table 436. Priority scheme for transmit and receive DMA . .
Table 437. Transmit descriptor word 0 (TDES0). . . . . . . 529
Table 438. Transmit descriptor word 1 (TDES1). . . . . . . 532
Table 439. Transmit descriptor word 2 (TDES2). . . . . . . 532
Table 440. Transmit descriptor word 3 (TDES3). . . . . . . 533
Table 441. Transmit descriptor word 6 (TDES6). . . . . . . 533
Table 442. Transmit descriptor word 7 (TDES7). . . . . . . 533
Table 443. Receive descriptor fields 0 (RDES0). . . . . . . 535
(MAC_ADDR0_HIGH, address 0x4001 0040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 493
(MAC_ADDR0_LOW, address 0x4001 0044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 494
(MAC_TIMESTP_CTRL, address 0x4001 0700)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 494
495
address 0x4001 1000) bit description . . . . . 496
(DMA_TRANS_POLL_DEMAND, address
0x4001 1004) bit description . . . . . . . . . . . . 498
(DMA_REC_POLL_DEMAND, address 0x4001
1008) bit description . . . . . . . . . . . . . . . . . . . 499
(DMA_REC_DES_ADDR, address 0x4001 100C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 499
(DMA_TRANS_DES_ADDR, address 0x4001
1010) bit description . . . . . . . . . . . . . . . . . . . 500
0x4001 1014) bit description . . . . . . . . . . . . 500
address 0x4001 1018) bit description . . . . . 503
address 0x4001 101C) bit description . . . . . 505
register (DMA_MFRM_BUFOF, address 0x4001
1020) bit description . . . . . . . . . . . . . . . . . . . 508
(DMA_REC_INT_WDT, address 0x4001 1024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 508
(DMA_CURHOST_TRANS_DES, address
0x4001 1048) bit description . . . . . . . . . . . . 509
(DMA_CURHOST_REC_DES, address 0x4001
104C) bit description . . . . . . . . . . . . . . . . . . 509
register (DMA_CURHOST_TRANS_BUF,
address 0x4001 1050) bit description . . . . . 509
(DMA_CURHOST_REC_BUF, address 0x4001
1054) bit description . . . . . . . . . . . . . . . . . . . 509
513
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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