LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 427

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.10.1 Queue head initialization
20.10.10.2 Operational model for setup transfers
from the queue head. Therefore, software is required to track all transfer descriptors since
pointers will no longer exist within the queue head once the dTD is retired (see
Section
In addition to the current and next pointers and the dTD overlay examined in section
Operational Model For Packet Transfers, the dQH also contains the following parameters
for the associated endpoint: Multiplier, Maximum Packet Length, Interrupt On Setup. The
complete initialization of the dQH including these fields is demonstrated in the next
section.
One pair of device queue heads must be initialized for each active endpoint. To initialize a
device queue head:
Remark: The DCD must only modify dQH if the associated endpoint is not primed and
there are no outstanding dTD’s.
As discussed in section Control Endpoint Operational Model
transfer requires special treatment by the DCD. A setup transfer does not use a dTD but
instead stores the incoming data from a setup packet in an 8-byte buffer within the dQH.
Upon receiving notification of the setup packet, the DCD should handle the setup transfer
as demonstrated here:
1. Copy setup buffer contents from dQH - RX to software buffer.
2. Acknowledge setup backup by writing a “1” to the corresponding bit in
3. Check for pending data or status dTD’s from previous control transfers and flush if any
4. Decode setup packet and prepare data phase [optional] and status phase transfer as
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Write the wMaxPacketSize field as required by the USB Chapter 9 or application
specific protocol.
Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO
endpoints, set the multiplier to 1,2, or 3 as required bandwidth and in conjunction with
the USB Chapter 9 protocol. Note: In FS mode, the multiplier field can only be 1 for
ISO endpoints.
Write the next dTD Terminate bit field to “1”.
Write the Halt bit in the status field to “0”.
ENDPTSETUPSTAT.
Remark: The acknowledge must occur before continuing to process the setup packet.
Remark: After the acknowledge has occurred, the DCD must not attempt to access
the setup buffer in the dQH – RX. Only the local software copy should be examined.
exist as discussed in section Flushing/De-priming an Endpoint.
Remark: It is possible for the device controller to receive setup packets before
previous control transfers complete. Existing control packets in progress must be
flushed and the new control packet completed.
require by the USB Specification Chapter 9 or application specific protocol.
Write the Active bit in the status field to “0”.
20.10.11.1).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
(Section
20.10.8), setup
UM10430
© NXP B.V. 2011. All rights reserved.
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