LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 785

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

35.1 How to read this chapter
35.2 Basic configuration
35.3 Features
<Document ID>
User manual
This chapter applies to parts LPC1850/30/20/10 Rev ‘A’.
The I
The I
Table 726. I2S clocking and power control
The I2S bus provides a standard communication interface for digital audio applications.
The I2S bus specification defines a 3-wire serial bus, having one data, one clock, and one
word select signal. The basic I2S connection has one master, which is always the master,
and one slave. The I2S interface provides a separate transmit and receive channel, each
of which can operate as either a master or a slave.
Clock to the I2S0 and I2S1 register
interface and I2S0/1 peripheral clock.
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UM10430
Chapter 35: LPC18xx I2S interface
Rev. 00.13 — 20 July 2011
See
The I2S0 is reset by the I2S0_RST (reset # 52).
The I2S1 is reset by the I2S1_RST (reset # 53).
The I2S0 interrupt is connected to slot # 28 in the NVIC.
The I2S1 interrupt is connected to slot # 29 in the NVIC.
For connecting the I2S receive and transmit lines to the GPDMA, use the DMAMUX
register in the CREG block (see
DMA Channel Configuration registers
See
timer and SCT inputs.
The I2S input can operate in both master and slave mode.
The I2S output can operate in both master and slave mode, independent of the I2S
input.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
Versatile clocking includes independent transmit and receive fractional rate
generators, and an ability to use a single clock input or output for a 4-wire mode.
2
2
S interface is available on all LPC18xx parts.
S interface is configured as follows:
Table 726
Table 37
All information provided in this document is subject to legal disclaimers.
for interconnections between the I2S transmit/receive lines and the
for clocking and power control.
Rev. 00.13 — 20 July 2011
Table
Base clock
BASE_APB1_CLK
(Section
35) and enable the GPDMA channel in the
16.6.20).
Branch clock
CLK_APB1_I2S
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
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