LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 814

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 754. CAN status register (STAT, address 0x400E 2004 (C_CAN0) and 0x400A 4004 (C_CAN1)) bit description
<Document ID>
User manual
Bit
2:0
3
4
Symbol
LEC
TXOK
RXOK
36.6.1.2 CAN status register
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0
1
0
1
Description
Last error code
Type of the last error to occur on the CAN bus.The LEC field holds a
code which indicates the type of the last error to occur on the CAN bus.
This field will be cleared to ‘0’ when a message has been transferred
(reception or transmission) without error. The unused code ‘111’ may be
written by the CPU to check for updates.
No error .
Stuff error : More than 5 equal bits in a sequence have occurred in a
part of a received message where this is not allowed.
Form error : A fixed format part of a received frame has the wrong
format.
AckError : The message this CAN core transmitted was not
acknowledged.
Bit1Error : During the transmission of a message (with the exception of
the arbitration field), the device wanted to send a HIGH/recessive level
(bit of logical value ‘1’), but the monitored bus value was
LOW/dominant.
Bit0Error : During the transmission of a message (or acknowledge bit,
or active error flag, or overload flag), the device wanted to send a
LOW/dominant level (data or identifier bit logical value ‘0’), but the
monitored Bus value was HIGH/recessive. During busoff recovery this
status is set each time a
sequence of 11 HIGH/recessive bits has been monitored. This enables
the CPU to monitor the proceeding of the busoff recovery sequence
(indicating the bus is not stuck at LOW/dominant or continuously
disturbed).
CRCError : The CRC checksum was incorrect in the message received.
Unused: No CAN bus event was detected (written by the CPU).
Transmitted a message successfully
This bit is reset by the CPU. It is never reset by the CAN controller.
Since this bit was reset by the CPU, no message has been successfully
transmitted.
Since this bit was last reset by the CPU, a message has been
successfully transmitted (error free and acknowledged by at least one
other node).
Received a message successfully
This bit is reset by the CPU. It is never reset by the CAN controller.
Since this bit was last reset by the CPU, no message has been
successfully transmitted.
Since this bit was last set to zero by the CPU, a message has been
successfully received independent of the result of acceptance filtering.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 36: LPC18xx C_CAN
UM10430
Reset
value
000
0
0
© NXP B.V. 2011. All rights reserved.
814 of 1164
Access
R/W
R/W
R/W