LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1158

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Chapter 32: LPC18xx USART0_2_3
32.1
32.2
32.3
32.4
32.5
32.5.1
32.5.2
32.5.3
32.5.4
32.5.5
32.5.6
32.5.6.1
32.5.7
32.5.8
32.5.9
32.5.10
32.5.10.1 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
32.5.10.2 Auto-baud modes . . . . . . . . . . . . . . . . . . . . . 725
32.5.11
32.5.12
32.5.12.1 Baud rate calculation . . . . . . . . . . . . . . . . . . 728
32.5.12.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR =
Chapter 33: LPC18xx UART1
33.1
33.2
33.3
33.4
33.5
33.5.1
33.5.2
33.5.3
33.5.4
33.5.5
33.5.6
33.5.6.1
33.5.7
33.5.8
33.5.9
33.5.9.1
33.5.9.2
33.5.10
33.5.11
<Document ID>
User manual
How to read this chapter . . . . . . . . . . . . . . . . 712
Basic configuration . . . . . . . . . . . . . . . . . . . . 712
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 713
Register description . . . . . . . . . . . . . . . . . . . 713
How to read this chapter . . . . . . . . . . . . . . . . 743
Basic configuration . . . . . . . . . . . . . . . . . . . . 743
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 744
Register description . . . . . . . . . . . . . . . . . . . 745
UART Receiver Buffer Register . . . . . . . . . . 715
UART Transmitter Holding Register . . . . . . 715
UART Divisor Latch LSB and MSB Registers . . .
715
UART Interrupt Enable Register . . . . . . . . . . 716
UART Interrupt Identification Register . . . . . 717
UART FIFO Control Register . . . . . . . . . . . . 719
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 720
UART receiver DMA . . . . . . . . . . . . . . . . . . . .720
UART transmitter DMA . . . . . . . . . . . . . . . . . .720
UART Line Control Register . . . . . . . . . . . . . 720
UART Line Status Register . . . . . . . . . . . . . 721
UART Scratch Pad Register . . . . . . . . . . . . 723
UART Auto-baud Control Register . . . . . . . . 723
IrDA Control Register (UART3) . . . . . . . . . . 726
UART Fractional Divider Register (U0FDR -
0x4000 8028) . . . . . . . . . . . . . . . . . . . . . . . . 727
9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
UART1 Receiver Buffer Register (when
DLAB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
UART1 Transmitter Holding Register (when
DLAB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
UART1 Divisor Latch LSB and MSB Registers
(when DLAB = 1) . . . . . . . . . . . . . . . . . . . . . 747
UART1 Interrupt Enable Register (when
DLAB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
UART1 Interrupt Identification Register . . . . 749
UART1 FIFO Control Register . . . . . . . . . . . 751
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 752
UART receiver DMA . . . . . . . . . . . . . . . . . . . .752
UART transmitter DMA . . . . . . . . . . . . . . . . . .752
UART1 Line Control Register . . . . . . . . . . . 752
UART1 Modem Control Register . . . . . . . . . 753
Auto-flow control . . . . . . . . . . . . . . . . . . . . . . 754
Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
UART1 Line Status Register . . . . . . . . . . . . 756
UART1 Modem Status Register . . . . . . . . . . 757
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
32.5.12.1.2 Example 2: UART_PCLK = 12 MHz, BR =
32.5.13
32.5.14
32.5.15
32.5.16
32.5.17
32.5.18
32.5.19
32.6
32.6.1
32.6.2
32.6.2.1
32.6.2.2
32.6.3
32.6.4
32.6.4.1
32.7
33.5.12
33.5.13
33.5.14
33.5.15
33.5.16
33.5.16.1 Baud rate calculation . . . . . . . . . . . . . . . . . . 762
33.5.16.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600 .
33.5.16.1.2 Example 2: PCLK = 12 MHz, BR = 115200 764
33.5.17
33.5.18
33.5.19
33.5.20
33.5.21
33.5.22
33.6
Functional description . . . . . . . . . . . . . . . . . 736
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 768
115200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
UART Half-duplex enable register . . . . . . . . 730
UART Smart card interface control register . 731
UART RS485 Control register . . . . . . . . . . . 732
UART RS485 Address Match register . . . . . 733
UART1 RS485 Delay value register. . . . . . . 734
UART Synchronous mode control register . 734
UART Transmit Enable Register . . . . . . . . . 736
Asynchronous mode . . . . . . . . . . . . . . . . . . 736
Synchronous mode . . . . . . . . . . . . . . . . . . . 736
Synchronous slave mode. . . . . . . . . . . . . . . 737
Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 737
Synchronous master mode . . . . . . . . . . . . . 738
RS-485/EIA-485 modes of operation . . . . . . 738
RS-485/EIA-485 Normal Multidrop Mode (NMM)
738
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
RS-485/EIA-485 Auto Direction Control. . . . . 739
RS485/EIA-485 driver delay time. . . . . . . . . . 739
RS485/EIA-485 output inversion . . . . . . . . . . 739
Smart card mode . . . . . . . . . . . . . . . . . . . . . 739
Smart card set-up procedure . . . . . . . . . . . . 740
UART1 Scratch Pad Register . . . . . . . . . . . 758
UART1 Auto-baud Control Register . . . . . . 758
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 759
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 760
UART1 Fractional Divider Register . . . . . . . 761
764
UART1 Transmit Enable Register . . . . . . . . 764
UART1 RS485 Control register . . . . . . . . . . 765
UART1 RS-485 Address Match register . . . 766
UART1 RS-485 Delay value register . . . . . 766
RS-485/EIA-485 modes of operation . . . . . . 766
RS-485/EIA-485 Normal Multidrop Mode (NMM)
766
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
RS-485/EIA-485 Auto Direction Control. . . . . 767
RS485/EIA-485 driver delay time. . . . . . . . . . 767
RS485/EIA-485 output inversion . . . . . . . . . . 768
UART1 FIFO Level register . . . . . . . . . . . . . 768
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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