LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 760

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
33.5.15 Auto-baud modes
The auto-baud interrupts have to be cleared by setting the corresponding U1ACR
ABTOIntClr and ABEOIntEn bits.
Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during
auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it
is going to impact the measuring of UART1 Rx pin baud-rate, but the value of the U1FDR
register is not going to be modified after rate measurement. Also, when auto-baud is used,
any write to U1DLM and U1DLL registers should be done before U1ACR register write.
The minimum and the maximum baud rates supported by UART1 are function of pclk,
number of data bits, stop bits and parity bits.
When the software is expecting an “AT” command, it configures the UART1 with the
expected character format and sets the U1ACR Start bit. The initial values in the divisor
latches U1DLM and U1DLM don‘t care. Because of the “A” or “a” ASCII coding
(”A" = 0x41, “a” = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected
character are delimited by two falling edges. When the U1ACR Start bit is set, the
auto-baud protocol will execute the following phases:
1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the
2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If
6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to
•
•
ratemin
The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn
is set and the auto-baud rate measurement counter overflows).
The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn
is set and the auto-baud has completed successfully).
UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate.
measuring counter will start counting pclk cycles optionally pre-scaled by the
fractional baud-rate generator.
the frequency of the (fractional baud-rate pre-scaled) UART1 input clock,
guaranteeing the start bit is stored in the U1RSR.
counter will continue incrementing with the pre-scaled UART1 input clock (pclk).
Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.
normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt
U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the
remaining bits of the “A/a” character.
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2 P
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16 2 15
 CLK
All information provided in this document is subject to legal disclaimers.

Rev. 00.13 — 20 July 2011
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UART
1
baudrate
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16
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2
+
databits
PCLK
+
Chapter 33: LPC18xx UART1
paritybits
+
UM10430
stopbits
© NXP B.V. 2011. All rights reserved.
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