LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 52

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
6.6.8 Set status register
Table 26.
Table 27.
Bit
16
18:17
19
31:20
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
WAKEUP0_SETST
WAKEUP1_SETST
WAKEUP2_SETST
WAKEUP3_SETST
ATIMER_SETST
RTC_SETST
BOD_SETST
WWDT_SETST
ETH_SETST
USB0_SETST
USB1_SETST
-
CAN_SETST
TIM2_SETST
TIM6_SETST
QEI_SETST
TIM14_SETST
Symbol
TIM14_CLRST
-
RESET_CLRST
-
Interrupt clear status register (CLR_STAT - address 0x4004 4FE8) bit description
Interrupt set status register (SET_STAT - address 0x4004 4FEC) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Writing a 1 to this bit sets the STATUS event bit 0 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 1 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 2 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 3 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 4 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 5 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 6 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 7 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 8 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 9 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 10 in the
STATUS register.
Reserved.
Writing a 1 to this bit sets the STATUS event bit 12 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 13 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 14 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 15 in the
STATUS register.
Writing a 1 to this bit sets the STATUS event bit 16 in the
STATUS register.
Description
Writing a 1 to this bit clears the STATUS event bit 16 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 19 in
the STATUS register.
Reserved.
Chapter 6: LPC18xx Event router
UM10430
© NXP B.V. 2011. All rights reserved.
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-
Reset
value
Reset
value