LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 620

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 529. SCT configuration example
<Document ID>
User manual
Configuration
Define when event 4
occurs
Define when event 5
occurs
Define when event 6
occurs
Define how event 6
changes the state
Define by which events
output 0 is set
Define by which events
output 0 is cleared
Define which event
resets the counter
Configure states event 0
is enabled
Configure states event 1
is enabled
Configure states event 2
is enabled
Configure states event 3
is enabled
Configure states event 4
is enabled
Configure states event 5
is enabled
Configure states event 6
is enabled
Register(s)
EVCTRL4
EVCTRL5
EVCTRL6
EVCTRL6
OUTPUTSET0
OUTPUTCLR0
LIMIT
EVSTATEMSK0
EVSTATEMSK1
EVSTATEMSK2
EVSTATEMSK3
EVSTATEMSK4
EVSTATEMSK5
EVSTATEMSK6
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Setting
Set STATEV bits to 0 and the STATED bit to 1. Event 6 changes the
state to state 0.
Set SET0 bits 0 (for event 0) and 4 (for event 4) to one to set the
output when these events 0 and 4 occur.
Set CLR0 bits 1 (for events 1) and 5 (for event 5) to one to clear the
output when events 1 and 5 occur.
Set LIMMASK_L bit 2 to 1 (for event 2 to limit the counter). Set all
other bits to zero.
Set STATEMSK0 bit 0 to 1. Set all other bits to 0. Event 0 is enabled
in state 0.
Set STATEMSK1 bit 0 to 1. Set all other bits to 0. Event 1 is enabled
in state 0.
Set STATEMSK2 bit 0 to 1 and bit 1 to 1. Set all other bits to 0. Event
2 is enabled in state 0 and state 1.
Set STATEMSK3 bit 0 to 1. Set all other bits to 0. Event 3 is enabled
in state 0.
Set STATEMSK4 bit 1 to 1. Set all other bits to 0. Event 4 is enabled
in state 1.
Set STATEMSK5 bit 1 to 1. Set all other bits to 0. Event 5 is enabled
in state 1.
Set STATEMSK6 bit 1 to 1. Set all other bits to 0. Event 6 is enabled
in state 1.
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•
•
•
•
•
•
Set COMBMODE = 0x1. Event 4 uses match condition only.
Set MATCHSEL = 0x3. Select match value of match register 4.
Set COMBMODE = 0x1. Event 5 uses match condition only.
Set MATCHSEL = 0x3. Select match value of match register 5.
Set COMBMODE = 0x2. Event 6 uses I/O condition only.
Set IOSEL = 0. Select input 0.
Set IOCOND = 0x1. Input 0 goes HIGH.
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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