LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 481

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 402. Register overview: Ethernet MAC and DMA (base address 0x4001 0000)
Table 403. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description
<Document ID>
User manual
Name
DMA_CURHOST_TRANS_BUF
DMA_CURHOST_REC_BUF
DMA_HW_FEATURE
Bit
1:0
2
3
4
Symbol
-
RE
TE
DF
22.6.1 MAC Configuration register
Description
Reserved
Receiver enable
When this bit is set, the receiver state machine of the MAC is enabled for receiving
frames from the MII. When this bit is reset, the MAC receive state machine is disabled
after the completion of the reception of the current frame, and will not receive any
further frames from the MII.
Transmitter Enable
When this bit is set, the transmit state machine of the MAC is enabled for
transmission on the MII. When this bit is reset, the MAC transmit state machine is
disabled after the completion of the transmission of the current frame, and will not
transmit any further frames.
Deferral Check
When this bit is set, the deferral check function is enabled in the MAC. The MAC will
issue a Frame Abort status, along with the excessive deferral error bit set in the
transmit frame status when the transmit state machine is deferred for more than
24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps
operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the
threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is
ready to transmit, but is prevented because of an active CRS (carrier sense) signal on
the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times,
then transmits, collides, backs off, and then has to defer again after completion of
back-off, the deferral timer resets to 0 and restarts.
When this bit is reset, the deferral check function is disabled and the MAC defers until
the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is
reserved (RO) in Full-Duplex-only configuration.
The MAC Configuration register establishes receive and transmit operating modes.
Access
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Address
offset
0x1050
0x1054
0x1058
Description
Current host transmit buffer address
register
Current host receive buffer address
register
HW feature register
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 0000
0x0000 0000
0x0105 2715
Reset
value
00
0
0
0
481 of 1164
Access
RO
R/W
R/W
R/W