LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 279

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 215. DMA Channel Configuration registers (CCONFIG, 0x4000 2110 (C0CONFIG) to 0x4000 21F0 (C7CONFIG))
<Document ID>
User manual
Bit
0
5:1
Symbol
E
SRCPERIPHERAL
bit description
Value
0
1
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Description
Channel enable. Reading this bit indicates whether a channel is
currently enabled or disabled:
The Channel Enable bit status can also be found by reading the
ENBLDCHNS Register.
A channel can be disabled by clearing the Enable bit. This
causes the current AHB transfer (if one is in progress) to
complete and the channel is then disabled. Any data in the FIFO
of the relevant channel is lost. Restarting the channel by setting
the Channel Enable bit has unpredictable effects, the channel
must be fully re-initialized.
The channel is also disabled, and Channel Enable bit cleared,
when the last LLI is reached, the DMA transfer is completed, or
if a channel error is encountered.
If a channel must be disabled without losing data in the FIFO,
the Halt bit must be set so that further DMA requests are
ignored. The Active bit must then be polled until it reaches 0,
indicating that there is no data left in the FIFO. Finally, the
Channel Enable bit can be cleared.
Channel disabled.
Channel enabled.
Source peripheral. This value selects the DMA source request
peripheral. This field is ignored if the source of the transfer is
from memory. See
Source = SPIFI
Source = Timer 0 match 0/UART0 transmit
Source = Timer 0 match 1/UART0 receive
Source = Timer 1 match 0/UART1 transmit
Source = Timer 1 match 1/UART 1 receive
Source = Timer 2 match 0/UART 2 transmit
Source = Timer 2 match 1/UART 2 receive
Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0
Source = Timer 3 match 1/UART3 receive/SCT DMA request 1
Source = SSP0 receive/I2S channel 0
Source = SSP0 transmit/I2S channel 1
Source = SSP1 receive
Source = SSP1 transmit
Source = ADC0
Source = ADC1
Source = DAC
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Table 195
for details.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
279 of 1164
Access
R/W
R/W