LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 493

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.6.13 MAC Interrupt mask register
22.6.14 MAC Address 0 high register
22.6.15 MAC Address 0 low register
Table 415. MAC Interrupt status register (MAC_INTR, address 0x4001 0038) bit description
The Interrupt Mask Register bits enables the user to mask the interrupt signal due to the
corresponding event in the Interrupt Status Register.
Table 416. MAC Interrupt mask register (MAC_INTR_MASK, address 0x4001 003C) bit
The MAC Address 0 High register holds the upper 16 bits of the 6-byte first MAC address
of the station. Note that the first DA byte that is received on the (G)MII interface
corresponds to the LS Byte (Bits [7:0]) of the MAC Address Low register. For example, if
0x112233445566 is received (0x11 is the first byte) on the (G)MII as the destination
address, then the MacAddress0 Register [47:0] is compared with 0x665544332211.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, then the synchronization is triggered only when Bits[31:24] (in Little-Endian
mode) or Bits[7:0] (in Big-Endian mode) of the MAC Address Low Register (Register 17)
are written to. Please note that consecutive writes to this Address Low Register should be
performed only after at least 4 clock cycles in the destination clock domain for proper
synchronization updates.
Table 417. MAC Address 0 high register (MAC_ADDR0_HIGH, address 0x4001 0040) bit
The MAC Address 0 Low register holds the lower 32 bits of the 6-byte first MAC address
of the station.
Bit
31:0
Bit
2:0
3
31:4
Bit
15:0
30:16
31
Symbol
-
Symbol
-
PMTMSK PMT Interrupt Mask
Symbol
A47_32
-
MO
description
description
All information provided in this document is subject to legal disclaimers.
Description
Reserved
Description
Reserved
This bit when set, will disable the assertion of the interrupt
signal due to the setting of PMT Interrupt Status bit in
Table
Reserved
Description
MAC Address0 [47:32]
This field contains the upper 16 bits (47:32) of the 6-byte
first MAC address. This is used by the MAC for filtering for
received frames and for inserting the MAC address in the
Transmit Flow Control (PAUSE) Frames.
Reserved
Always 1
Rev. 00.13 — 20 July 2011
415.
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0xFFFF R/W
0x0000 RO
1
Reset
value
0
Reset
value
0
0
0
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Access
RO
Access
RO
R/W
R/W
Access
RO