LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 904

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
38.6.4 A/D Data Registers
38.6.5 A/D Status register
Table 831. A/D Interrupt Enable register (INTEN - address 0x400E 300C (ADC0) and
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 832. A/D Data registers (DR - addresses 0x400E 3010 (DR0) to 0x400E 302C (DR7)
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the AD0/1DRn register for each A/D
channel n are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is
also found in ADSTAT.
Bit
7:0
8
31:9 -
Bit
5:0
15:6
29:16 -
30
31
Symbol
ADINTEN
ADGINTEN
Symbol
-
V_VREF
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
DONE
0x400E 400C (ADC1)) bit description
(ADC0); 0x400E 4010 (DR0) to 0x400E 402C (DR7) (ADC1)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Reserved. Always 0.
When DONE is 1, this field contains a binary fraction representing the
voltage on the ADCn input pin selected in
voltage on the VDDA pin. Zero in the field indicates that the voltage on
the ADCn input pin was less than, equal to, or close to that on VDDA,
while 0x3FF indicates that the voltage on ADCn input pin was close to,
equal to, or greater than that on VDDA.
Reserved. Always 0.
was (were) lost and overwritten before the conversion that produced
the result in the V_VREF bits in this register.This bit is cleared by
reading this register.
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
Description
These bits allow control over which A/D channels generate
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
Reserved. Always 0.
Rev. 00.13 — 20 July 2011
Chapter 38: LPC18xx 10-bit ADC0/1
Table
829, divided by the
UM10430
© NXP B.V. 2011. All rights reserved.
904 of 1164
Reset
value
0x00
1
0
Reset
value
0
-
0
0
0