LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 77

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
9.6.3.4 PLL0 (for USB) NP-divider register
9.6.4.1 PLL0 (for audio) status register
9.6.4.2 PLL0 (for audio) control register
9.6.4 PLL0 (for audio) registers
Table 53.
Table 54.
See
Table 55.
Table 56.
Bit
21:17
27:22
31:28
Bit
6:0
11:7
21:12
31:22
Bit
0
1
31:2
Bit
0
1
Section 9.7.4.5
Symbol
PD
BYPASS
Symbol
SELP
SELI
SELR
Symbol
PDEC
-
NDEC
-
Symbol
LOCK
FR
-
PLL0USB M-divider register (PLL0USB_MDIV, address 0x4005 0024) bit
description
PLL0USB NP-divider register (PLL0USB_NP_DIV, address 0x4005 0028) bit
description
PLL0AUDIO status register (PLL0AUDIO_STAT, address 0x4005 002C) bit
description
PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit
description
…continued
All information provided in this document is subject to legal disclaimers.
for instructions on how to set up the PLL0.
Description
Bandwidth select P value
Bandwidth select I value
Bandwidth select R value
Description
Decoded P-divider coefficient value
Reserved
Decoded N-divider coefficient value
Reserved
Rev. 00.13 — 20 July 2011
Description
PLL0 lock indicator
PLL0 free running indicator
Reserved
Value
0
1
0
1
Description
PLL0 power down
PLL0 enabled
PLL0 powered down
Input clock bypass control
CCO clock sent to post-dividers. Use this
in normal operation.
PLL0 input clock sent to post-dividers
(default).
Chapter 9: LPC18xx Clock Generation Unit (CGU)
000 0010
Reset
value
-
1011 0001 R/W
-
UM10430
Reset
value
0
0
Reset
value
11100
010111
0000
© NXP B.V. 2011. All rights reserved.
Reset
value
1
1
R
-
Access
R
Access
R/W
-
-
Access
R/W
R/W
Access
R/W
R/W
R/W
77 of 1164