LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 774

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
34.6.3 SSP Data Register
Table 717: SSP Control Register 1 (CR1 - address 0x4008 3004 (SSP0), 0x400C 5004 (SSP1))
Software can write data to be transmitted to this register, and read data that has been
received.
Table 718: SSP Data Register (DR - address 0x4008 3008 (SSP0), 0x400C 5008 (SSP1)) bit
Bit
0
1
2
3
31:4
Bit
15:0
31:16 -
Symbol Description
DATA
Symbol Value Description
LBM
SSE
MS
SOD
-
bit description
description
All information provided in this document is subject to legal disclaimers.
0
1
0
1
0
1
Write: software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1, indicating that
the Tx FIFO is not full. If the Tx FIFO was previously empty and the
SSP controller is not busy on the bus, transmission of the data will
begin immediately. Otherwise the data written to this register will be
sent as soon as all previous data has been sent (and received). If the
data length is less than 16 bits, software must right-justify the data
written to this register.
Read: software can read data from this register whenever the RNE bit
in the Status register is 1, indicating that the Rx FIFO is not empty.
When software reads this register, the SSP controller returns data from
the least recent frame in the Rx FIFO. If the data length is less than 16
bits, the data is right-justified in this field with higher order bits filled with
0s.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Loop Back Mode.
During normal operation.
Serial input is taken from the serial output (MOSI or MISO) rather
than the serial input pin (MISO or MOSI respectively).
SSP Enable.
The SSP controller is disabled.
The SSP controller will interact with other devices on the serial
bus. Software should write the appropriate control information to
the other SSP registers and interrupt controller registers, before
setting this bit.
Master/Slave Mode.This bit can only be written when the SSE bit
is 0.
The SSP controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
The SSP controller acts as a slave on the bus, driving MISO line
and receiving SCLK, MOSI, and SSEL lines.
Slave Output Disable. This bit is relevant only in slave mode
(MS = 1). If it is 1, this blocks this SSP controller from driving the
transmit data line (MISO).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 34: LPC18xx SSP0/1
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x0000
NA
Reset
value
0
0
0
0
NA