LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 343

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.23 Static Memory Output Enable Delay registers
19.7.24 Static Memory Read Delay registers
19.7.25 Static Memory Page Mode Read Delay registers
The StaticWaitOen registers enable you to program the delay from the chip select or
address change, whichever is later, to the output enable. It is recommended that these
registers are modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. These registers are accessed with one wait state.
Table 289. Static Memory Output Enable delay registers (STATICWAITOEN, address
The StaticWaitRd registers enable you to program the delay from the chip select to the
read access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. It
is not used if the extended wait bit is enabled in the StaticConfig registers. These registers
are accessed with one wait state.
Table 290. Static Memory Read Delay registers (STATICWAITRD, address 0x4000 520C
[1]
The StaticWaitPage registers enable you to program the delay for asynchronous page
mode sequential accesses. It is recommended that these registers are modified during
system initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This register is accessed with one wait state.
Bit
3:0
31:4
Bit
4:0
31:5
The reset value is 0x0B for the STATICWAITRD0 register only.
Symbol
WAITRD Non-page mode read wait states or asynchronous page mode read first
-
Symbol
WAITOEN
-
0x4000 5208 (STATICWAITOEN0), 0x4000 5228 (STATICWAITOEN1), 0x4000 5248
(STATICWAITOEN2), 0x4000 5268 (STATICWAITOEN3)) bit description
(STATICWAITRD0), 0x4000 522C (STATICWAITRD1), 0x4000 524C
(STATICWAITRD2), 0x4000 526C (STATICWAITRD3)) bit description
All information provided in this document is subject to legal disclaimers.
Description
access wait state.
Non-page mode read or asynchronous page mode read, first read only:
0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For
non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK.
0x1F = 32 CCLK cycles for read accesses (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Wait output enable.
Delay from chip select assertion to output enable.
0x0 = No delay (POR reset value).
0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0xB
[1]
-
Reset
value
0x0
-