LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 341

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 287. Static Memory Configuration registers (STATICCONFIG, address 0x4000 5200
Bit
1:0
2
3
5:4
6
7
Symbol
MW
-
PM
-
PC
PB
(STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240
(STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0x0
0x1
0x2
0x3
-
0
1
-
0
1
0
1
Rev. 00.13 — 20 July 2011
Memory width.
8 bit (POR reset value).
16 bit.
32 bit.
Reserved.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Page mode.
In page mode the EMC can burst up to four external accesses.
Therefore devices with asynchronous page mode burst four or
higher devices are supported. Asynchronous page mode burst
two devices are not supported and must be accessed normally.
Disabled (POR reset value).
Async page mode enabled (page length four).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chip select polarity.
The value of the chip select polarity on power-on reset is 0.
Active LOW chip select.
Active HIGH chip select.
Byte lane state.
The byte lane state bit, PB, enables different types of memory to
be connected. For byte-wide static memories the BLSn[3:0]
signal from the EMC is usually connected to WE (write enable).
In this case for reads all the BLSn[3:0] bits must be HIGH. This
means that the byte lane state (PB) bit must be LOW.
16 bit wide static memory devices usually have the BLSn[3:0]
signals connected to the UBn and LBn (upper byte and lower
byte) signals in the static memory. In this case a write to a
particular byte must assert the appropriate UBn or LBn signal
LOW. For reads, all the UB and LB signals must be asserted
LOW so that the bus is driven. In this case the byte lane state
(PB) bit must be HIGH.
Remark: When PB is set to 0, the WE signal is undefined or 0.
You must set PB to 1, to use the WE signal.
For reads all the bits in BLSn[3:0] are HIGH. For writes the
respective active bits in BLSn[3:0] are LOW (POR reset value).
For reads the respective active bits in BLSn[3:0] are LOW. For
writes the respective active bits in BLSn[3:0] are LOW.
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
-
0
-
0
0