LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 702

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
31.6.1 Interrupt Location Register
31.6.2 Clock Control Register
The Interrupt Location Register is a 2-bit register that specifies which blocks are
generating an interrupt (see
corresponding interrupt. Writing a zero has no effect. This allows the programmer to read
this register and write back the same value to clear only the interrupt that is detected by
the read.
Table 634. Interrupt Location Register (ILR - address 0x4004 6000) bit description
The clock register is a 4-bit register that controls the operation of the clock divide circuit.
Each bit of the clock register is described in
should be initialized when the RTC is first turned on.
Table 635. Clock Control Register (CCR - address 0x4004 6008) bit description
[1]
Bit
0
1
31:2
Bit
0
1
3:2
4
31:5
This register value is not changed by reset.
Symbol
RTCCIF
RTCALF
-
Symbol
CLKEN
CTCRST
-
CCALEN
-
All information provided in this document is subject to legal disclaimers.
Description
When one, the Counter Increment Interrupt block generated an
interrupt. Writing a one to this bit location clears the counter increment
interrupt.
When one, the alarm registers generated an interrupt. Writing a one to
this bit location clears the alarm interrupt.
value read from a reserved bit is not defined.
Value Description
0
1
0
1
0
1
Reserved, user software should not write ones to reserved bits. The
Rev. 00.13 — 20 July 2011
Clock Enable.
The time counters are disabled so that they may be initialized.
The time counters are enabled.
CTC Reset.
No effect.
When one, the elements in the internal oscillator divider are
reset, and remain reset until CCR[1] is changed to zero. This is
the divider that generates the 1 Hz clock from the 32.768 kHz
crystal. The state of the divider is not visible to software.
Internal test mode controls. These bits must be 0 for normal
RTC operation.
Calibration counter enable.
The calibration counter is enabled and counting, using the
1 Hz clock. When the calibration counter is equal to the value
of the CALIBRATION register, the counter resets and repeats
counting up to the value of the CALIBRATION register. See
Section 31.6.6.2
The calibration counter is disabled and reset to zero.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Table
634). Writing a one to the appropriate bit clears the
and
Chapter 31: LPC18xx Real-Time Clock (RTC)
Section
Table
635. Bits 0, 1, and 4 in this register
31.7.1.
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
NA
Reset
value
-
0
-
-
NA
[1]
[1]
[1]