LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 749

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 694: UART1 Interrupt Enable Register when DLAB = 0 (IER - address 0x4008 2004 ) bit description
Table 695: UART1 Interrupt Identification Register (IIR - address 0x4008 2008) bit description
<Document ID>
User manual
Bit
7
8
9
31:10 -
Bit
0
3:1
5:4
7:6
Symbol
CTSIE
ABEOIE
ABTOIE
Symbol
INTSTATUS
INTID
-
FIFOENABL
E
33.5.5 UART1 Interrupt Identification Register
Value Description
Value Description
0
0x3
0
1
0
1
0
1
0x2
0x6
0x1
0x0
The U1IIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during
an U1IIR access, the interrupt is recorded for the next U1IIR access.
1
CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem
status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a
CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (U1IER[3])
is set.
In normal operation a CTS1 signal transition will generate a Modem Status Interrupt
unless the interrupt has been disabled by clearing the U1IER[3] bit in the U1IER
register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both
the U1IER[3] and U1IER[7] bits are set.
Disable the CTS interrupt.
Enable the CTS interrupt.
Enables the end of auto-baud interrupt.
Disable end of auto-baud Interrupt.
Enable end of auto-baud Interrupt.
Enables the auto-baud time-out interrupt.
Disable auto-baud time-out Interrupt.
Enable auto-baud time-out Interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be
determined by evaluating U1IIR[3:1].
At least one interrupt is pending.
No interrupt is pending.
Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the
UART1 Rx or TX FIFO. All other combinations of U1IER[3:1] not listed below
are reserved (100,101,111).
1 - Receive Line Status (RLS).
2a - Receive Data Available (RDA).
2b - Character Time-out Indicator (CTI).
3 - THRE Interrupt.
4 - Modem Interrupt.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Copies of U1FCR[0].
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 33: LPC18xx UART1
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
1
0
NA
0
749 of 1164
Reset
value
0
0
0
NA