LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 613

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.7.6 Clearing the prescaler
24.7.7 Match vs. I/O events
When enabled by a non-zero PRE field in the Control register, the prescaler acts as a
clock divider for the counter, like a fractional part of the counter value. The prescaler is
cleared whenever the counter is cleared or loaded for any of the following reasons:
When BIDIR is 0, a limit event caused by an I/O signal can clear a non-zero prescaler, but
a limit event caused by a Match will only clear a non-zero prescaler in one special case as
described
A limit event when BIDIR is 1 does not clear the prescaler. Rather it clears the DOWN bit
in the Control register, and decrements the counter on the same clock if the counter is
enabled in that clock.
Counter operation is complicated by the prescaler, and by clock mode 01 in which the
SCT clock is the bus clock, but the prescaler and counter are enabled to count only when
a selected edge is detected on a clock input.
An I/O component of an event can occur in any SCT clock when its counter’s HALT bit is
0. In general a Match component of an event can only occur in a UT clock when its
counter’s HALT and STOP bits are both 0 and the counter is enabled.
Table 527
Table 527. Event conditions
COMBMODE IOMODE
IO
MATCH
OR
AND
AND
•
•
•
•
•
•
Hardware reset
Software writing to the counter register
Software writing a 1 to the CLRCTR bit in the control register
an event selected by a 1 in the counter’s limit register when BIDIR = 0
The prescaler is enabled when the clock mode is not 01, or when the input edge
selected by the CLKSEL field is detected.
The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the
prescaler is equal to the value in PRELIM).
Section
shows when the various kinds of events can occur.
Any
Any
Any
LOW or HIGH
RISE or FALL
All information provided in this document is subject to legal disclaimers.
24.7.7.
Rev. 00.13 — 20 July 2011
Event can occur on clock:
Event can occur whenever HALT = 0 (type A).
Event can occur when HALT = 0 and STOP = 0 and the counter is
enabled (type C).
From the IO component: Event can occur whenever HALT = 0 (A).
From the match component: Event can occur when HALT = 0 and
STOP = 0 and the counter is enabled (C).
Event can occur when HALT = 0 and STOP = 0 and the counter is
enabled (C).
Event can occur whenever HALT = 0 (A).
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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