LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 979

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
The CGU contains four types of clock generators:
The output stages select a clock source from the clock source bus for each base clock
(see
(BASE_USB0_CLK), the clock source for each output stage can be any of the external
and internal clocks and oscillators directly or one of the PLL outputs or any of the outputs
of the integer dividers.
Table 926. CGU0 base clocks
Number Name
0
1
2
3
4
5
6
7
8
9
10
11
12
1. External clock inputs and internal clocks: The external clock inputs are the Ethernet
2. Crystal oscillator: The crystal oscillator is controlled by the CGU. The input to the
3. PLLs: PLL0 and PLL1 are controlled by the CGU. Each PLL can select one input from
4. Integer dividers: Each of the five integer dividers can select one input from the clock
PHY clocks and the general purpose input clock GP_CLKIN. The clocks from the
internal oscillators are the IRC and the 32 kHz oscillator output clocks. These clock
generators have no selectable inputs from the clock source bus and provide one clock
output each to the clock source bus.
crystal oscillator are the XTAL pins. The crystal oscillator creates one output to the
clock source bus.
the clock source bus and provides one output to the clock source bus. The input to the
PLL can be selected from all external and internal clocks and oscillators, from the
other PLL, and from the outputs of any of the integer dividers (see
source bus and creates one divided output clock to the clock source bus. The input to
all integer dividers can be selected from all external and internal clocks and
oscillators, and from both PLLs. In addition, the output of the first integer divider can
be selected as an input to all other integer dividers (see
dividers have different programmable division ratios:
– Integer divider A: maximum division factor = 4 (see
– Integer dividers B, C, D: maximum division factor = 16 (see
– Integer divider E: maximum division factor = 256 (see
Table
BASE_SAFE_CLK
BASE_USB0_CLK
-
BASE_USB1_CLK
BASE_M3_CLK
BASE_SPIFI_CLK
-
BASE_PHY_RX_CLK
BASE_PHY_TX_CLK
BASE_APB1_CLK
BASE_APB3_CLK
BASE_LCD_CLK
-
928). Except for the base clocks to the WWDT (BASE_SAFE_CLK) and USB0
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Frequency
[1]
12 MHz
480 MHz
-
150 MHz
150 MHz
150 MHz
-
75 MHz
75 MHz
150 MHz
150 MHz
150 MHz
-
Description
Base safe clock (always on) for WDT
Base clock for USB0
Reserved.
Base clock for USB1
core and APB peripheral blocks #0 and #2
Base clock for SPIFI
Reserved.
Base clock for Ethernet PHY Rx
Base clock for Ethernet PHY Tx
Base clock for APB peripheral block # 1
Base clock for APB peripheral block # 3
Base clock for LCD
Reserved
System base clock for ARM Cortex-M3
Table
Table
Table
939).
Chapter 42: Appendix
927). The integer
Table
941).
UM10430
Table
© NXP B.V. 2011. All rights reserved.
940).
927).
979 of 1164