LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1162

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
40.8.15
40.9
40.9.1
40.9.2
40.9.3
40.9.4
40.9.5
40.9.6
40.9.7
40.9.8
40.9.9
40.9.10
Chapter 41: LPC18xx JTAG, Serial Wire Debug (SWD), and trace functions
41.1
41.2
41.3
41.4
Chapter 42: Appendix
42.1
42.1.1
42.1.2
42.1.3
42.1.4
42.1.5
42.1.6
42.1.7
42.1.8
42.1.8.1
42.1.8.2
42.1.8.3
42.1.8.4
42.1.8.5
42.1.8.6
42.1.8.7
42.1.8.8
42.1.8.9
42.1.8.10 Interrupt Priority Register 4 . . . . . . . . . . . . . 955
42.1.8.11 Interrupt Priority Register 5 . . . . . . . . . . . . . 955
42.1.8.12 Interrupt Priority Register 6. . . . . . . . . . . . . . 955
42.1.8.13 Interrupt Priority Register 7 . . . . . . . . . . . . . 956
42.1.8.14 Software Trigger Interrupt Register (STIR -
42.2
42.2.1
42.2.2
42.2.3
42.2.4
42.2.5
42.2.6
42.2.6.1
42.2.6.2
<Document ID>
User manual
IAP commands . . . . . . . . . . . . . . . . . . . . . . . . 925
How to read this chapter . . . . . . . . . . . . . . . . 935
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
LPC1850/30/20/10 Rev ‘-’ Event router. . . . . 957
LPC1850/30/20/10 Rev ‘-’ NVIC . . . . . . . . . . 938
ISP Return Codes. . . . . . . . . . . . . . . . . . . . . 923
Prepare sector(s) for write operation . . . . . . 926
Copy RAM to Flash . . . . . . . . . . . . . . . . . . . 927
Erase Sector(s). . . . . . . . . . . . . . . . . . . . . . . 928
Blank check sector(s) . . . . . . . . . . . . . . . . . . 928
Read part identification number . . . . . . . . . . 928
Read Boot Code version number . . . . . . . . . 929
Read device serial number . . . . . . . . . . . . . . 929
Compare <address1> <address2> <no of bytes>
929
Re-invoke ISP. . . . . . . . . . . . . . . . . . . . . . . . 930
IAP Status Codes . . . . . . . . . . . . . . . . . . . . . 930
How to read this chapter. . . . . . . . . . . . . . . . 938
Basic configuration . . . . . . . . . . . . . . . . . . . . 938
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
General description . . . . . . . . . . . . . . . . . . . 938
Pin description . . . . . . . . . . . . . . . . . . . . . . . 938
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . 939
Vector table remapping. . . . . . . . . . . . . . . . . 940
Examples: . . . . . . . . . . . . . . . . . . . . . . . . . . . .940
Register description . . . . . . . . . . . . . . . . . . . 941
Interrupt Clear-Enable Register 0 . . . . . . . . 944
Interrupt Active Bit Register 0 . . . . . . . . . . . 951
Interrupt Priority Register 0 . . . . . . . . . . . . . 953
Interrupt Priority Register 1 . . . . . . . . . . . . . 953
Interrupt Priority Register 2. . . . . . . . . . . . . . 954
Interrupt Priority Register 3 . . . . . . . . . . . . . 954
0xE000 EF00). . . . . . . . . . . . . . . . . . . . . . . . 956
How to read this chapter. . . . . . . . . . . . . . . . 957
Basic configuration . . . . . . . . . . . . . . . . . . . . 957
General description . . . . . . . . . . . . . . . . . . . 957
Event router inputs . . . . . . . . . . . . . . . . . . . . 958
Pin description . . . . . . . . . . . . . . . . . . . . . . . 958
Register description . . . . . . . . . . . . . . . . . . . 958
Level configuration register . . . . . . . . . . . . . 959
Edge configuration register. . . . . . . . . . . . . . 961
. . . Interrupt Set-Enable Register 0 register 942
. . Interrupt Set-Pending Register 0 register 946
. Interrupt Clear-Pending Register 0 register 949
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
40.10
40.11
40.11.1
40.11.1.1 Signature generation address and control
40.11.1.2 Signature generation result registers . . . . . . 932
40.11.1.3 Flash Module Status register (FMSTAT -
40.11.1.4 Flash Module Status Clear register (FMSTATCLR
40.11.2
41.5
41.6
41.7
41.8
42.2.6.3
42.2.6.4
42.2.6.5
42.2.6.6
42.2.6.7
42.2.6.8
42.3
42.3.1
42.3.2
42.3.3
42.3.4
42.3.4.1
42.3.4.2
42.3.4.3
42.3.4.4
42.3.4.5
42.3.4.6
42.3.4.7
42.3.4.8
42.3.4.9
42.4
42.4.1
42.4.2
42.4.3
42.4.4
42.4.5
42.4.6
42.4.6.1
42.4.6.2
42.4.6.3
42.4.6.3.1 PLL0 status register . . . . . . . . . . . . . . . . . . . 986
42.4.6.3.2 PLL0 control register . . . . . . . . . . . . . . . . . . 986
42.4.6.3.3 PLL0 M-divider register . . . . . . . . . . . . . . . . 987
42.4.6.3.4 PLL0 NP-divider register . . . . . . . . . . . . . . . 987
JTAG flash programming interface . . . . . . . 930
Flash signature generation . . . . . . . . . . . . . 931
Pin Description . . . . . . . . . . . . . . . . . . . . . . . 935
Debug Notes . . . . . . . . . . . . . . . . . . . . . . . . . 936
Debug memory re-mapping . . . . . . . . . . . . . 937
JTAG TAP Identification . . . . . . . . . . . . . . . . 937
LPC1850/30/20/10 Rev ‘-’ CREG . . . . . . . . . 970
LPC1850/30/20/10 Rev ‘-’ CGU . . . . . . . . . . 977
Register description for signature generation 931
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
0x0x4008 4FE0). . . . . . . . . . . . . . . . . . . . . . 933
- 0x0x4008 4FE8) . . . . . . . . . . . . . . . . . . . . 933
Algorithm and procedure for signature generation
934
Signature generation . . . . . . . . . . . . . . . . . . . 934
Content verification . . . . . . . . . . . . . . . . . . . . 934
Interrupt clear enable register . . . . . . . . . . . 964
Event set enable register . . . . . . . . . . . . . . . 965
Event status register . . . . . . . . . . . . . . . . . . 966
Event enable register . . . . . . . . . . . . . . . . . . 967
Clear status register. . . . . . . . . . . . . . . . . . . 968
Set status register . . . . . . . . . . . . . . . . . . . . 969
How to read this chapter . . . . . . . . . . . . . . . 970
Basic configuration. . . . . . . . . . . . . . . . . . . . 970
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Register description . . . . . . . . . . . . . . . . . . . 971
IRC trim register. . . . . . . . . . . . . . . . . . . . . . 971
CREG0 control register . . . . . . . . . . . . . . . . 972
Power mode control register . . . . . . . . . . . . 972
ARM Cortex-M3 memory mapping register . 973
CREG5 control register . . . . . . . . . . . . . . . . 973
DMA muxing register . . . . . . . . . . . . . . . . . . 973
ETB SRAM configuration register . . . . . . . . 976
CREG6 control register . . . . . . . . . . . . . . . . 976
Part ID register. . . . . . . . . . . . . . . . . . . . . . . 977
How to read this chapter . . . . . . . . . . . . . . . 977
Basic configuration. . . . . . . . . . . . . . . . . . . . 978
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
General description . . . . . . . . . . . . . . . . . . . 978
Pin description . . . . . . . . . . . . . . . . . . . . . . . 982
Register description . . . . . . . . . . . . . . . . . . . 982
Frequency monitor register . . . . . . . . . . . . . 983
Crystal oscillator control register . . . . . . . . . 985
PLL0 (for USB0) registers . . . . . . . . . . . . . . 986
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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