LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 599

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.10 SCT match/capture registers mode register
Table 508. SCT input register (INPUT - address 0x4000 0048) bit description
If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used, and they
control whether each set of match/capture registers operate as unified 32-bit
capture/match registers.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
REGMODE_L (address 0x4000 404C) and REGMODE_H (address 0x4000 404E). Both
the L and H registers can be read or written in a single 32-bit read or write operation, or
they can be read or written individually. The _L bits/registers control the L match/capture
registers, and the _H bits/registers control the H match/capture registers.
The SCT contains 16 Match/Capture register pairs. The Register Mode register selects
whether each register pair acts as a Match register (see
register (see
register which serves as a Reload register when the register is used as a Match register
(Section
register
An alternate addressing mode is available for all of the Match/Capture and
Reload/Capture-Control registers, for DMA access to halfword registers when UNIFY=0. It
is described in
Bit
0
1
2
3
4
5
6
7
15:8
16
17
18
19
20
21
22
23
31:24
Symbol
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
-
SIN0
SIN1
SIN2
SIN3
SIN4
SIN5
SIN6
SIN7
-
(Section
24.6.21) or as a Capture-Control register when the register is used as a capture
Section
Section
All information provided in this document is subject to legal disclaimers.
24.6.22). REGMODE_H is used only when the UNIFY bit is 0.
Description
Real-time status of input 0.
Real-time status of input 1.
Real-time status of input 2.
Real-time status of input 3.
Real-time status of input 4.
Real-time status of input 5.
Real-time status of input 6.
Real-time status of input 7.
Reserved.
Input 0 state synchronized to the SCT clock.
Input 1 state synchronized to the SCT clock.
Input 2 state synchronized to the SCT clock.
Input 3 state synchronized to the SCT clock.
Input 4 state synchronized to the SCT clock.
Input 5 state synchronized to the SCT clock.
Input 6 state synchronized to the SCT clock.
Input 7 state synchronized to the SCT clock.
Reserved
24.6.20). Each Match/Capture register has an accompanying
Rev. 00.13 — 20 July 2011
24.7.9.
Chapter 24: LPC18xx State Configurable Timer (SCT)
Section
24.6.19) or as a Capture
UM10430
© NXP B.V. 2011. All rights reserved.
599 of 1164
Reset
value
pin
pin
pin
pin
pin
pin
pin
pin
-
-
-
-
-
-
-
-
-
-