LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 837

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
36.7 Functional description
<Document ID>
User manual
36.6.4.1 CAN clock divider register
36.6.4 CAN timing register
36.7.1 C_CAN controller state after reset
Table 793. CAN message valid 2 register (MSGV2, address 0x400E 2164 (C_CAN0) and
This register determines the CAN clock signal. The CAN_CLK is derived from the
peripheral clock PCLK divided by the values in this register.
Table 794. CAN clock divider register (CLKDIV, address 0x400E 2180 (C_CAN0) and 0x400A
After a hardware reset, the registers hold the values described in
the busoff state is reset and the output CAN_TXD is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.
Bit
15:0
31:16 -
Bit
3:0
31:4
Symbol
MSGVAL32_17 Message valid bits of message objects 32 to 17.
Symbol
CLKDIVVAL Clock divider value
-
0x400A 4164 (C_CAN1)) bit description
4180 (C_CAN1)) bit description
All information provided in this document is subject to legal disclaimers.
Description
CAN_CLK = PCLK/(2
0000: CAN_CLK = PCLK divided by 1.
0001: CAN_CLK = PCLK divided by 2.
0010: CAN_CLK = PCLK divided by 3.
0010: CAN_CLK = PCLK divided by 4.
0011: CAN_CLK = PCLK divided by 5.
0100: CAN_CLK = PCLK divided by 9.
0101: CAN_CLK = PCLK divided by 17.
...
1111: CAN_CLK = PCLK divided by 16385.
reserved
Rev. 00.13 — 20 July 2011
Description
0 = This message object is ignored by the message
handler.
1 = This message object is configured and should
be considered by the message handler.
Reserved
CLKDIVVAL -1
+1)
Chapter 36: LPC18xx C_CAN
Table
UM10430
© NXP B.V. 2011. All rights reserved.
751. Additionally,
Access Reset
R
-
Reset
value
0000
-
837 of 1164
value
0x00
-
Access
R/W
-