LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 654

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.7.9.6 MCPWM Interrupt Flags clear address
Table 566. MCPWM Interrupt Flags set address (INTF_SET - 0x400A 006C) bit description
Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus
clearing the corresponding interrupt request(s). This is typically done in interrupt service
routines.
Table 567. MCPWM Interrupt Flags clear address (INTF_CLR - 0x400A 0070) bit description
Bit
8
9
10
14:11 -
15
31:16 -
Bit
0
1
2
3
4
5
6
7
8
9
10
14:11 -
15
31:16 -
Symbol
ILIM2_F_SET
IMAT2_F_SET
ICAP2_F_SET
ABORT_F_SET Writing a one sets the corresponding bit in the INTF register,
Symbol
ILIM0_F_CLR
IMAT0_F_CLR
ICAP0_F_CLR
-
ILIM1_F_CLR
IMAT1_F_CLR
ICAP1_F_CLR
-
ILIM2_F_CLR
IMAT2_F_CLR
ICAP2_F_CLR
ABORT_F_CLR
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Reserved.
thus possibly simulating hardware interrupt.
Reserved.
Writing a one clears the corresponding bit in INTEN, thus
Description
Writing a one clears the corresponding bit in the INTF register,
thus clearing the corresponding interrupt request.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Reserved.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Reserved.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.
disabling the interrupt.
Reserved.
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
-
-
-
-
-
-
Reset
value
-
-
-
-
-
-
-
-
-
-
-
-
-
-