LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 76

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
9.6.3.3 PLL0 (for USB) M-divider register
Table 52.
Table 53.
Bit
3
4
5
6
7
8
9
10
11
23:12
28:24
31:29
Bit
16:0
Symbol
DIRECTO
CLKEN
-
FRM
-
-
-
-
AUTOBLOCK
-
CLK_SEL
-
Symbol
MDEC
PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description
PLL0USB M-divider register (PLL0USB_MDIV, address 0x4005 0024) bit
description
…continued
All information provided in this document is subject to legal disclaimers.
Description
Decoded M-divider coefficient value. Select values for
the M-divider between 1 and 131071.
Rev. 00.13 — 20 July 2011
Value
0
1
0x00
0x01
0x02
0x03
0x04
0x06
0x09
0x0C
0x0D
0x0E
0x0F
0x10
Description
PLL0 direct output
PLL0 clock enable
Reserved
Free running mode
Reserved
Reserved. Reads as zero. Do not write
one to this register.
Reserved. Reads as zero. Do not write
one to this register.
Reserved. Reads as zero. Do not write
one to this register.
Block clock automatically during frequency
change
Autoblocking disabled
Autoblocking enabled
Reserved
Clock source selection. All other values
are reserved.
32 kHz oscillator
IRC (default)
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
Crystal oscillator
PLL1
IDIVA
IDIVB
IDIVC
IDIVD
IDIVE
Reserved
Chapter 9: LPC18xx Clock Generation Unit (CGU)
UM10430
Reset
value
0x5B6A
© NXP B.V. 2011. All rights reserved.
0
Reset
value
0
-
0
0
0
0
0
0
-
0x01
-
Access
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
-
Access
R/W
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