LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 405

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
20.9 Device data structures
<Document ID>
User manual
20.8.3.1.2 Port speed detection
design that can count the 10ms reset pulse to alleviate the requirement of the software to
measure this duration. Therefore, the basic connection is then summarized as the
following:
After the port change interrupt indicates that a port is enabled, the EHCI stack should
determine the port speed. Unlike the EHCI implementation which will re-assign the port
owner for any device that does not connect at High-Speed, this host controller supports
direct attach of non High-Speed devices. Therefore, the following differences are
important regarding port speed detection:
This section defines the interface data structures used to communicate control, status,
and data between Device Controller Driver (DCD) Software and the Device Controller.
The data structure definitions in this chapter support a 32-bit memory buffer address
space.
Remark: The Software must ensure that no interface data structure reachable by the
Device controller crosses a 4k-page boundary
The data structures defined in the chapter are (from the device controller’s perspective) a
mix of read-only and read/ writable fields. The device controller must preserve the
read-only fields on all data structure writes.
•
•
•
•
•
•
•
[Port Change Interrupt] Port connect change occurs to notify the host controller driver
that a device has attached.
Software shall write a ‘1’ to the reset the device.
Software shall write a ‘0’ to the reset the device after 10 ms.
This step, which is necessary in a standard EHCI design, may be omitted with this
implementation. Should the EHCI host controller driver attempt to write a ‘0’ to the
reset bit while a reset is in progress the write will simple be ignored and the reset will
continue until completion.
the device in now operational and at this point the port speed has been determined.
Port Owner is read-only and always reads 0.
operating speed of the port to the host controller driver.
A 1-bit High Speed indicator has been added to PORTSC to signify that the port is in
High-Speed vs. Full/Low Speed – This information is redundant with the 2-bit Port
Speed indicator above.
[Port Change Interrupt] Port enable change occurs to notify the host controller that
A 2-bit Port Speed indicator has been added to PORTSC to provide the current
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
405 of 1164