LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 751

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 696: UART1 Interrupt Handling
Table 697: UART1 FIFO Control Register (FCR - address 0x4008 2008) bit description
<Document ID>
User manual
U1IIR[3:0]
value
1100
0010
0000
Bit
0
[1]
Symbol
FIFOEN
Priority Interrupt
Second Character
Third
Fourth
33.5.6 UART1 FIFO Control Register
Type
Time-out
indication
THRE
Modem
Status
Value Description
0
1
[1]
[2]
[3]
[4]
The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated
when the UART1 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART1 THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U1THR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U1THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART1 THR FIFO has held two or more characters at one time and
currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or
a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.
The write-only U1FCR controls the operation of the UART1 RX and TX FIFOs.
Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
For details see
For details see
For details see
Transmitter Holding Register (when DLAB = 0)”
FIFO enable.
Must not be used in the application.
Active high enable for both UART1 Rx and TX FIFOs and U1FCR[7:1] access.
This bit must be set for proper UART1 operation. Any transition on this bit will
automatically clear the UART1 FIFOs.
Interrupt Source
Minimum of one character in the RX FIFO and no
character input or removed during a time period depending
on how many characters are in FIFO and what the trigger
level is set at (3.5 to 4.5 character times).
The exact time will be:
[(word length)  7 - 2]  8 + [(trigger level - number of
characters)  8 + 1] RCLKs
THRE
CTS or DSR or RI or DCD
[2]
All information provided in this document is subject to legal disclaimers.
Section 33.5.10 “UART1 Line Status Register”
Section 33.5.1 “UART1 Receiver Buffer Register (when DLAB = 0)”
Section 33.5.5 “UART1 Interrupt Identification Register”
Rev. 00.13 — 20 July 2011
Chapter 33: LPC18xx UART1
and
Interrupt Reset
U1RBR Read
U1IIR Read
interrupt) or THR write
MSR Read
Section 33.5.2 “UART1
UM10430
© NXP B.V. 2011. All rights reserved.
[4]
[3]
(if source of
Reset value
0
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