LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 890

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
37.11 Software example
<Document ID>
User manual
37.10.10 The state service routines
37.10.11 Adapting state services to an application
37.10.8 Initialization
37.10.9 I
37.11.1 Initialization routine
37.11.2 Start Master Transmit function
In the initialization example, the I
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:
The I
Call. If the General Call or the own slave address is detected, an interrupt is requested
and STAT is loaded with the appropriate state information.
When the I
26 state services to be executed.
Each state routine is part of the I
The state service examples show the typical actions that must be performed in response
to the 26 I
associated state services can be omitted, as long as care is taken that the those states
can never occur.
In an application, it may be desirable to implement some kind of time-out during I
operations, in order to trap an inoperative bus or a lost service routine.
Example to initialize I
Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then
initiating a START.
2
1. Load ADR with own Slave Address, enable General Call recognition if needed.
2. Enable I
3. Write 0x44 to CONSET to set the I2EN and AA bits, enabling Slave functions. For
1. Initialize Master data counter.
•
•
•
C interrupt service
I2ADR is loaded with the part’s own slave address and the General Call bit (GC)
The I
The slave mode is enabled by simultaneously setting the I2EN and AA bits in CON
and the serial clock frequency (for master modes) is defined by is defined by loading
the
Master only functions, write 0x40 to CONSET.
2
C hardware now begins checking the I
SCLH and SCLL registers
2
2
C interrupt enable and interrupt priority bits are set
2
C state codes. If one or more of the four I
C interrupt is entered, STAT contains a status code which identifies one of the
2
C interrupt.
All information provided in this document is subject to legal disclaimers.
2
C Interface as a Slave and/or Master.
Rev. 00.13 — 20 July 2011
. The master routines must be started in the main program.
2
2
C interrupt routine and handles one of the 26 states.
C block is enabled for both master and slave modes.
2
C-bus for its own slave address and General
Chapter 37: LPC18xx I2C-bus interface
2
C operating modes are not used, the
UM10430
© NXP B.V. 2011. All rights reserved.
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2
C