LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 38

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
5.7 Register description
Table 14.
<Document ID>
User manual
Name
ISER0
ISER1
ICER0
Access Address
RW
RW
RW
Register overview: NVIC (base address 0xE000 E000)
offset
0x100
0x104
0x180
Table 13.
The following table summarizes the registers in the NVIC as implemented in the LPC18xx.
The Cortex-M3 User Guide provides a functional description of the NVIC.
Interrupt
ID
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Interrupt Set-Enable Register 0. This register allows enabling interrupts and
Interrupt Set-Enable Register 1. This register allows enabling interrupts and
Description
reading back the interrupt enables for specific peripheral functions.
reading back the interrupt enables for specific peripheral functions.
Interrupt Clear-Enable Register 0. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions.
Exception
Number
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Connection of interrupt sources to the NVIC
All information provided in this document is subject to legal disclaimers.
Vector
Offset
0xB4
0xB8
0xBC
0xC0
0xC4
0xC8
0xCC
0xD0
0xC4
0xC8
0xCC
0xD0
0xD4
0xD8
0xDC
0xE0
0xE4
0xE8
0xEC
0xF0
0xF4
0xF8
0xFC
0x100
Rev. 00.13 — 20 July 2011
Function
I2S1
SPIFI
-
GPIO pin interrupt 0
GPIO pin interrupt 1
GPIO pin interrupt 2
GPIO pin interrupt 3
GPIO pin interrupt 4
GPIO pin interrupt 5
GPIO pin interrupt 6
GPIO pin interrupt 7
GPIO group interrupt 0
GPIO group interrupt 1
Event router
C_CAN1 interrupt
Reserved
Reserved
ATIMER
Reserved
Reserved
WWDT
Reserved
C_CAN0
QEI
Flag(s)
Reserved
Combined interrupt from the event
router sources
Chapter 5: LPC18xx NVIC
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0