LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1056

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.8.4.1 GPIO port direction register (DIR)
Table 980. Register overview: GPIO (register base address: 0x400F 0000)
[1]
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. The direction bit for any pin must be set according to the pin
functionality.
Reading returns the status of the DIR register.
Table 981. GPIO port direction register (DIR0 to DIR4 - addresses 0x400F 0000 to 0x400F
Aside from the 32-bit long and word only accessible DIR register, every GPIO port can
also be controlled via two byte and one half-word accessible register listed in
Next to providing the same functions as the DIR register, these additional registers allow
easier and faster access to the physical port pins.
Name
-
MASK4
PIN4
SET4
CLR4
Bit
15:0
31:16
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
DIRPIN
-
0080) bit description
All information provided in this document is subject to legal disclaimers.
Access Address
-
R/W
R/W
R/W
W
Description
GPIO direction port x (x = 0 to 4) control bits. Bit 0 controls pin
GPIOx_0, bit 15 controls pin GPIOx_15.
0 = Controlled pin is input.
1 = Controlled pin is output.
Reserved.
Rev. 00.13 — 20 July 2011
0x090
0x094
0x098
offset
0x084 to
0x08C
0x09C
Description
Reserved.
GPIO port 4 mask register for port access.
GPIO port 4 pin value register using MASK.
GPIO port 4 output set register using MASK4.
This register controls the state of output pins. Only
bits enabled by 0 in MASK4 can be altered.
GPIO port 4 output clear register using MASK4.
This register controls the state of output pins. Only
bits enabled by 0 in MASK4 can be altered.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
…continued
Reset value
0x0
-
Table
1056 of 1164
Reset
value
-
0x0
0x0
0x0
0x0
982.
[1]