LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 330

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 269. Dynamic Control register (DYNAMICCONTROL - address 0x4000 5020) bit
[1]
[2]
[3]
Remark: Deep-sleep mode can be entered by setting the deep-sleep mode (DP) bit, the
dynamic memory clock enable bit (CE), and the dynamic clock control bit (CS) to one. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
Bit
1
2
4:3
5
6
8:7
12:9
13
31:14 -
Clock enable must be HIGH during SDRAM initialization.
The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional
mode set this bit LOW.
Disabling CLKOUT can be performed if there are no SDRAM memory transactions. When enabled this bit
can be used in conjunction with the dynamic memory clock control (CS) field.
Symbol
-
-
-
CS
SR
MMC
I
DP
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
-
0
1
-
0x0
0x1
0x2
0x3
-
0
1
-
Rev. 00.13 — 20 July 2011
Dynamic memory clock control. When clock control is LOW the
output clock CLKOUT is stopped when there are no SDRAM
transactions. The clock is also stopped during self-refresh mode.
CLKOUT stops when all SDRAMs are idle and during
self-refresh mode.
CLKOUT runs continuously (POR reset value).
Self-refresh request, EMCSREFREQ. By writing 1 to this bit
self-refresh can be entered under software control. Writing 0 to
this bit returns the EMC to normal mode.
The self-refresh acknowledge bit in the Status register must be
polled to discover the current operating mode of the EMC.
Normal mode.
Enter self-refresh mode (POR reset value).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Memory clock control.
CLKOUT enabled (POR reset value).
CLKOUT disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
SDRAM initialization.
Issue SDRAM NORMAL operation command (POR reset value).
Issue SDRAM MODE command.
Issue SDRAM PALL (precharge all) command.
Issue SDRAM NOP (no operation) command)
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Low-power SDRAM deep-sleep mode.
Normal operation (POR reset value).
Enter Deep-sleep mode.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 19: LPC18xx External Memory Controller (EMC)
[3]
UM10430
© NXP B.V. 2011. All rights reserved.
[2]
330 of 1164
Reset
value
1
1
-
0
-
00
-
0
-