LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 68

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
The output stages select a clock source from the clock source bus for each base clock
(see
(BASE_USB0_CLK), the clock source for each output stage can be any of the external
and internal clocks and oscillators directly or one of the PLL outputs or any of the outputs
of the integer dividers.
Table 44.
[1]
Table 45
Number Name
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21-24
25
26
27
– Integer divider A: maximum division factor = 4 (see
– Integer dividers B, C, D: maximum division factor = 16 (see
– Integer divider E: maximum division factor = 256 (see
Maximum frequency that guarantees stable operation of the LPC18xx.
Table
shows all available input clock sources for each clock generator.
BASE_SAFE_CLK
BASE_USB0_CLK
-
BASE_USB1_CLK
BASE_M3_CLK
BASE_SPIFI_CLK
-
BASE_PHY_RX_CLK
BASE_PHY_TX_CLK
BASE_APB1_CLK
BASE_APB3_CLK
BASE_LCD_CLK
BASE_ENET_CSR_CLK
BASE_SDIO_CLK
BASE_SSP0_CLK
BASE_SSP1_CLK
BASE_UART0_CLK
BASE_UART1_CLK
BASE_UART2_CLK
BASE_UART3_CLK
BASE_OUT_CLK
-
BASE_APLL_CLK
BASE_CGU_OUT0_CLK
BASE_CGU_OUT1_CLK
CGU0 base clocks
46). Except for the base clocks to the WWDT (BASE_SAFE_CLK) and USB0
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 9: LPC18xx Clock Generation Unit (CGU)
Frequency
[1]
12 MHz
480 MHz
-
150 MHz
150 MHz
150 MHz
150 MHz
75 MHz
75 MHz
150 MHz
150 MHz
150 MHz
<tbd>
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
-
150 MHz
150 MHz
150 MHz
Description
Base safe clock (always on) for WDT
Base clock for USB0
Reserved
Base clock for USB1
core and APB peripheral blocks #0 and #2
Base clock for SPIFI
Reserved
Base clock for Ethernet PHY Rx
Base clock for Ethernet PHY Tx
Base clock for APB peripheral block # 1
Base clock for APB peripheral block # 3
Base clock for LCD
Base clock for <tbd>
Base clock for SD/MMC
Base clock for SSP0
Base clock for SSP1
Base clock for UART0
Base clock for UART1
Base clock for UART2
Base clock for UART3
Base clock for CLKOUT pin
Reserved
Base clock for audio PLL
Base clock for CGU_OUT0 clock output
Base clock for CGU_OUT1 clock output
System base clock for ARM Cortex-M3
Table
Table
62).
Table
64).
UM10430
© NXP B.V. 2011. All rights reserved.
63).
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