LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 326

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 265. Register overview: External memory controller (base address 0x4000 5000)
<Document ID>
User manual
Name
DYNAMICXSR
DYNAMICRRD
DYNAMICMRD
-
STATICEXTENDEDWAIT
-
DYNAMICCONFIG0
DYNAMICRASCAS0
-
DYNAMICCONFIG1
DYNAMICRASCAS1
-
DYNAMICCONFIG2
DYNAMICRASCAS2
-
DYNAMICCONFIG3
DYNAMICRASCAS3
-
STATICCONFIG0
STATICWAITWEN0
STATICWAITOEN0
STATICWAITRD0
STATICWAITPAGE0
STATICWAITWR0
STATICWAITTURN0
STATICCONFIG1
STATICWAITWEN1
Access Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
-
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
offset
0x050
0x054
0x058
0x05C -
0x07C
0x080
-
0x100
0x104
0x108 -
0x11C
0x120
0x124
0x128 -
0x13C
0x140
0x144
0x148 -
0x15C
0x160
0x164
0x168 -
0x1FC
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x220
0x224
All information provided in this document is subject to legal disclaimers.
Description
Selects the exit self-refresh to active command time.
Selects the active bank A to active bank B latency.
Selects the load mode register to active command time.
Reserved.
Selects time for long static memory read and write
transfers.
Reserved.
Selects the configuration information for dynamic memory
chip select 0.
Selects the RAS and CAS latencies for dynamic memory
chip select 0.
Reserved.
Selects the configuration information for dynamic memory
chip select 1.
Selects the RAS and CAS latencies for dynamic memory
chip select 1.
Reserved.
Selects the configuration information for dynamic memory
chip select 2.
Selects the RAS and CAS latencies for dynamic memory
chip select 2.
Reserved.
Selects the configuration information for dynamic memory
chip select 3.
Selects the RAS and CAS latencies for dynamic memory
chip select 3.
Reserved.
Selects the memory configuration for static chip select 0.
Selects the delay from chip select 0 to write enable.
Selects the delay from chip select 0 or address change,
whichever is later, to output enable.
Selects the delay from chip select 0 to a read access.
Selects the delay for asynchronous page mode sequential
accesses for chip select 0.
Selects the delay from chip select 0 to a write access.
Selects the number of bus turnaround cycles for chip select
0.
Selects the memory configuration for static chip select 1.
Selects the delay from chip select 1 to write enable.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 001F
0x0000 000F
0x0000 000F
-
0x0
-
0x0
0x0000 0303
-
0x0
0x0000 0303
-
0x0
0x0000 0303
-
0x0
0x0000 0303
-
0x0
0x0
0x0
0x0000 0007
0x0000 001F
0x0000 001F
0x0000 000F
0x0
0x0
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