LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1126

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 194. GPDMA clocking and power control . . . . . . .263
Table 195. Peripheral connections to the DMA controller and
Table 196. Register overview: GPDMA (base address
Table 197. DMA Interrupt Status register (INTSTAT, address
Table 198. DMA Interrupt Terminal Count Request Status
Table 199. DMA Interrupt Terminal Count Request Clear
Table 200. DMA Interrupt Error Status
Table 201. DMA Interrupt Error Clear
Table 202. DMA Raw Interrupt Terminal Count Status
Table 203. DMA Raw Error Interrupt Status
Table 204. DMA Enabled Channel Register (ENBLDCHNS,
Table 205. DMA Software Burst Request Register
Table 206. DMA Software Single Request
Table 207. DMA Software Last Burst Request
Table 208. DMA Software Last Single Request
Table 209. DMA Configuration Register (CONFIG, address
Table 210. DMA Synchronization Register (SYNC, address
Table 211. DMA Channel Source Address Registers
Table 212. DMA Channel Destination Address
Table 213. DMA Channel Linked List Item registers (CLLI,
Table 214. DMA Channel Control registers (CCONTROL,
Table 215. DMA Channel Configuration registers
<Document ID>
User manual
level-sensitive pins . . . . . . . . . . . . . . . . . . . .262
matching flow control signals . . . . . . . . . . . . .264
0x4000 2000) . . . . . . . . . . . . . . . . . . . . . . . .267
0x4000 2000) bit description . . . . . . . . . . . . .269
Register (INTTCSTAT, address 0x4000 2004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Register (INTTCCLEAR, address 0x4000 2008)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .269
Register (INTERRSTAT, address 0x4000 200C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .270
Register (INTERRCLR, address 0x4000 2010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .270
Register (RAWINTTCSTAT, address 0x4000
2014) bit description . . . . . . . . . . . . . . . . . . . .270
Register (RAWINTERRSTAT, address 0x4000
2018) bit description . . . . . . . . . . . . . . . . . . . .271
address 0x4000 201C) bit description . . . . . .271
(SOFTBREQ, address 0x4000 2020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .272
Register (SOFTSREQ, address 0x4000 2024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .272
Register (SOFTLBREQ, address 0x4000 2028)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .273
Register (SOFTLSREQ, address 0x4000 202C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .273
0x4000 2030) bit description
0x4000 2034) bit description . . . . . . . . . . . . .274
(CSRCADDR, 0x4000 2100 (C0SRCADDR) to
0x4000 21E0 (C7SRCADDR)) bit description 275
registers (CDESTADDR, 0x4000 2104
(C0DESTADDR) to 0x4000 21E4
(C7DESTADDR)) bit description . . . . . . . . . .275
0x4000 2108 (C0LLI) to 0x4000 21E8 (C7LLI)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .276
0x4000 210C (C0CONTROL) to 0x4000 21EC
(C7CONTROL)) bit description . . . . . . . . . . .276
. . . . . . . . . . . .273
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 216. Flow control and transfer type bits . . . . . . . . 281
Table 217. Endian behavior . . . . . . . . . . . . . . . . . . . . . . 283
Table 218. DMA request signal usage . . . . . . . . . . . . . . 288
Table 219. SPIFI clocking and power control . . . . . . . . . 294
Table 220. SPIFI flash memory map. . . . . . . . . . . . . . . . 295
Table 221. SPIFI Pin description. . . . . . . . . . . . . . . . . . . 295
Table 222. SDIO clocking and power control . . . . . . . . . 296
Table 223. SDIO pin description . . . . . . . . . . . . . . . . . . . 297
Table 224. Register overview: SDMMC (base address:
Table 225. Control Register (CTRL, address 0x4000 4000)
Table 226. Power Enable Register (PWREN, address
Table 227. Clock Divider Register (CLKDIV, address 0x4000
Table 228. SD Clock Source Register (CLKSRC, address
Table 229. Clock Enable Register (CLKENA, address
Table 230. Time-out Register (TMOUT, address 0x4000
Table 231. Card Type Register (CTYPE, address 0x4000
Table 232. Block Size Register (BLKSIZ, address 0x4000
Table 233. Byte Count Register (BYTCNT, address 0x4000
Table 234. Interrupt Mask Register (INTMASK, address
Table 235. Command Argument Register (CMDARG,
Table 236. Command Register (CMD, address 0x4000
Table 237. Response Register 0 (RESP0, address 0x4000
Table 238. Response Register 1 (RESP1, address 0x4000
Table 239. Response Register 2 (RESP2, address 0x4000
Table 240. Response Register 3 (RESP3, address 0x4000
Table 241. Masked Interrupt Status Register (MINTSTS,
Table 242. Raw Interrupt Status Register (RINTSTS,
Table 243. Status Register (STATUS, address 0x4000 4048)
Table 244. FIFO Threshold Watermark Register (FIFOTH,
Table 245. Card Detect Register (CDETECT, address
Table 246. Write Protect Register (WRTPRT, address
Table 247. General Purpose Input/Output Register (GPIO,
(CCONFIG, 0x4000 2110 (C0CONFIG) to 0x4000
21F0 (C7CONFIG)) bit description
0x4000 4000) . . . . . . . . . . . . . . . . . . . . . . . . . 298
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 299
0x4000 4004) bit description . . . . . . . . . . . . . 301
4008) bit description. . . . . . . . . . . . . . . . . . . . 302
0x4000 400C) bit description . . . . . . . . . . . . . 302
0x4000 4010) bit description . . . . . . . . . . . . . 303
4014) bit description. . . . . . . . . . . . . . . . . . . . 303
4018) bit description. . . . . . . . . . . . . . . . . . . . 304
401C) bit description . . . . . . . . . . . . . . . . . . . 304
4020) bit description. . . . . . . . . . . . . . . . . . . . 304
0x4000 4024) bit description . . . . . . . . . . . . . 304
address 0x4000 4028) bit description . . . . . . 305
402C) bit description . . . . . . . . . . . . . . . . . . . 306
4030) bit description. . . . . . . . . . . . . . . . . . . . 309
4034) bit description. . . . . . . . . . . . . . . . . . . . 309
4038) bit description. . . . . . . . . . . . . . . . . . . . 309
403C) bit description . . . . . . . . . . . . . . . . . . . 309
address 0x4000 4040) bit description . . . . . . 309
address 0x4000 4044) bit description . . . . . . 310
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 312
address 0x4000 404C) bit description . . . . . . 313
0x4000 4050) bit description . . . . . . . . . . . . . 315
0x4000 4054) bit description . . . . . . . . . . . . . 315
address 0x4000 4058) bit description . . . . . . 315
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
. . . . . . . 279
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