LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 484

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 403. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description
Table 404. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description
<Document ID>
User manual
Bit
22
23
31:24
Bit
0
1
2
3
4
5
Symbol
JD
WD
-
Symbol
PR
-
-
DAIF
PM
DBF
22.6.2 MAC Frame filter register
Description
Jabber Disable
When this bit is set, the MAC disables the jabber timer on the transmitter, and can
transfer frames of up to 16,384 bytes.
When this bit is reset, the MAC cuts off the transmitter if the application sends out
more than 2,048 bytes of data (10,240 if JE is set high) during transmission.
Watchdog Disable
When this bit is set, the MAC disables the watchdog timer on the receiver, and can
receive frames of up to 16,384 bytes.
When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set
high) of the frame being received and cuts off any bytes received after that.
Reserved.
Description
Promiscuous Mode
When this bit is set, the Address Filter module passes all incoming frames regardless
of its destination or source address. The SA/DA Filter Fails status bits of the Receive
Status Word will always be cleared when PR is set.
reserved
reserved
DA Inverse Filtering
When this bit is set, the Address Check block operates in inverse filtering mode for
the DA address comparison for both unicast and multicast frames.
When reset, normal filtering of frames is performed.
Pass All Multicast
When set, this bit indicates that all received frames with a multicast destination
address (first bit in the destination address field is '1') are passed.
When reset, filtering of multicast frame depends on HMC bit.
Disable Broadcast Frames
When this bit is set, the AFM module filters all incoming broadcast frames.
When this bit is reset, the AFM module passes all received broadcast frames.
The MAC Frame Filter register contains the filter controls for receiving frames. Some of
the controls from this register go to the address check block of the MAC, which performs
the first level of address filtering. The second level of filtering is performed on the
incoming frame, based on other controls such as Pass Bad Frames and Pass Control
Frames.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0x00
Reset
value
0
0
0
0
0
0
484 of 1164
Access
R/W
R/W
RO
Access
R/W
RO
RO
R/W
R/W
R/W