LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1068

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 996. Transmit FIFO register (TXFIFO - address 0x400A 2008) bit description
Table 997. I2S Receive FIFO register (RXFIFO - address 0x400A 200C) bit description
Table 998. I2S Status Feedback register (STATE - address 0x400A 2010) bit description
<Document ID>
User manual
Bit
31:0
Bit
31:0 I2SRXFIFO
Bit
0
1
2
7:3
11:8
15:12
19:16
31:20
Symbol
Symbol
I2STXFIFO
Symbol
IRQ
DMAREQ1
DMAREQ2
-
RX_LEVEL
-
TX_LEVEL
-
42.9.6.4 Receive FIFO register
42.9.6.5 I2S Status Feedback register
42.9.6.6 I2S DMA Configuration Register 1
Description
8 x 32-bit transmit FIFO.
Description
8 x 32-bit transmit FIFO.
Description
This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined
by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ
register.
This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by
comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the
DMA1 register.
This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by
comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the
DMA2 register.
Reserved.
Reflects the current level of the Receive FIFO.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Reflects the current level of the Transmit FIFO.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The I2SRXFIFO register provides access to the receive FIFO. The function of bits in
I2SRXFIFO are shown in
The STATE register provides status information about the I2S interface. The meaning of
bits in STATE are shown in
The DMA1 register controls the operation of DMA request 1. The function of bits in DMA1
are shown in
controller”
This register enables the DMA for the I
FIFO level.
Remark: The FIFOs contain eight 16-bit words. Therefore, if the I
configured for 32-bit mode (see
level is 4.
for details of DMA operation.
Table
All information provided in this document is subject to legal disclaimers.
999. Refer to
Rev. 00.13 — 20 July 2011
Table
Table
997.
Table 994
Chapter 16 “LPC18xx General Purpose DMA (GPDMA)
998.
2
S receive and transmit channels and sets the
and
Table
995), the maximum allowed FIFO
2
Chapter 42: Appendix
S controller is
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
Reset value
0
0
1068 of 1164
Reset
value
1
1
1
0
0
-
0
-