LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 559

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.6.18 Cursor Palette register 0
23.6.19 Cursor Palette register 1
The contents of the CRSR_CFG register are described in
Table 472. Cursor Configuration register (CRSR_CFG, address 0x4000 8C04) bit description
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color0 maps through CRSR_PAL0.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
The contents of the CRSR_PAL0 register are described in
Table 473. Cursor Palette register 0 (CRSR_PAL0, address 0x4000 8C08) bit description
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color1 maps through CRSR_PAL1.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
The contents of the CRSR_PAL1 register are described in
Bits
0
1
31:2
Bits
7:0
15:8
23:16
31:24
Function
CrsrSize
FRAMESYNC Cursor frame synchronization type.
-
Function
RED
GREEN
BLUE
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Cursor size selection.
0 = 32x32 pixel cursor. Allows for 4 defined cursors.
1 = 64x64 pixel cursor.
0 = Cursor coordinates are asynchronous.
1 = Cursor coordinates are synchronized to the frame
synchronization pulse.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Red color component
Green color component
Blue color component.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Table
Table
Table
Chapter 23: LPC18xx LCD
472.
473.
474.
UM10430
© NXP B.V. 2011. All rights reserved.
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0x0
0x0
Reset
value
0x0
0x0
-
Reset
value
0x0
-