LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 79

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
9.6.4.3 PLL0 (for audio) M-divider register
9.6.4.4 PLL0 (for audio) NP-divider register
9.6.4.5 PLL0 (for audio) fractional divider register
9.6.5.1 PLL1 status register
9.6.5 PLL1 registers
Table 57.
Table 58.
Table 59.
The PLL1 is used for the core and all peripheral blocks.
Table 60.
Bit
16:0
21:17
27:22
31:28
Bit
6:0
11:7
21:12
31:22
Bit
21:0
31:22
Bit
0
31:1
Symbol
MDEC
SELP
SELI
SELR
Symbol
PDEC
-
NDEC
-
Symbol
LOCK
-
Symbol
PLLFRACT_CTRL
-
PLL0AUDIO M-divider register (PLL0AUDIO_MDIV, address 0x4005 0034) bit
description
PLL0 AUDIO NP-divider register (PLL0AUDIO_NP_DIV, address 0x4005 0038) bit
description
PLL0AUDIO fractional divider register (PLL0AUDIO_FRAC, address 0x4005 003C)
bit description
PLL1 status register (PLL1_STAT, address 0x4005 0040) bit description
All information provided in this document is subject to legal disclaimers.
Description
Decoded M-divider coefficient value. Select values for
the M-divider between 1 and 131071.
Bandwidth select P value
Bandwidth select I value
Bandwidth select R value
Description
Decoded P-divider coefficient value
Reserved
Decoded N-divider coefficient value
Reserved
Rev. 00.13 — 20 July 2011
Description
PLL1 lock indicator
Reserved
Description
PLL fractional divider control word
Reserved
Chapter 9: LPC18xx Clock Generation Unit (CGU)
Reset
value
000 0000
-
000 0010
Reset
value
-
1011 0001 R/W
-
UM10430
Reset
value
0x5B6A
11100
010111
0000
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
-
Access
R/W
Access
R
-
Access
R/W
-
-
Access
R/W
R/W
R/W
R/W
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