LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 489

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 410. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description
<Document ID>
User manual
Bit
0
1
2
3
5:4
6
7
15:8
31:16
Symbol
FCB
TFE
RFE
UP
PLT
-
DZPQ
-
PT
Description
Flow Control Busy/Backpressure Activate
This bit initiates a Pause Control frame in Full-Duplex mode.
In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control
register. To initiate a Pause control frame, the Application must set this bit to 1. During
a transfer of the Control Frame, this bit will continue to be set to signify that a frame
transmission is in progress. After the completion of Pause control frame transmission,
the MAC will reset this bit to 0. The Flow Control register should not be written to until
this bit is cleared.
In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is
asserted by the MAC Core. During backpressure, when the MAC receives a new
frame, the transmitter starts sending a JAM pattern resulting in a collision. This control
register bit is logically OR’ed with the mti_flowctrl_i input signal for the backpressure
function. When the MAC is configured to Full- Duplex mode, the BPA is automatically
disabled.
Transmit Flow Control Enable
In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation
to transmit Pause frames. When this bit is reset, the flow control operation in the MAC
is disabled, and the MAC will not transmit any Pause frames.
In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure
operation. When this bit is reset, the backpressure feature is disabled.
Receive Flow Control Enable
When this bit is set, the MAC will decode the received Pause frame and disable its
transmitter for a specified (Pause Time) time. When this bit is reset, the decode
function of the Pause frame is disabled.
Unicast Pause Frame Detect
When this bit is set, the MAC will detect the Pause frames with the station’s unicast
address specified in MAC Address0 High Register and MAC Address0 Low Register,
in addition to the detecting Pause frames with the unique multicast address. When
this bit is reset, the MAC will detect only a Pause frame with the unique multicast
address specified in the 802.3x standard.
Pause Low Threshold
This field configures the threshold of the PAUSE timer at which the input flow control
is checked for automatic retransmission of PAUSE Frame. The threshold values
should be always less than the Pause Time configured in Bits[31:16]. For example, if
PT = Ox100 (256 slot-times), and PLT = 01, then a second PAUSE frame is
automatically transmitted if the flow control signal is asserted at 228 (256 – 28)
slot-times after the first PAUSE frame is transmitted.
Reserved
Disable Zero-Quanta Pause
When set, this bit disables the automatic generation of Zero-Quanta Pause Control
frames on the deassertion of the flow-control signal from the FIFO layer . When this
bit is reset, normal operation with automatic Zero-Quanta Pause Control frame
generation is enabled.
Reserved
Pause time
This field holds the value to be used in the Pause Time field in the transmit control
frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII
clock domain, then consecutive writes to this register should be performed only after
at least 4 clock cycles in the destination clock domain.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
00
0x000 RO
0
0
0x000
0
489 of 1164
Access
R/WS/
SC
R/W
R/W
R/W
R/W
R/W
RO
R/W