LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1159

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Chapter 34: LPC18xx SSP0/1
34.1
34.2
34.3
34.4
34.5
34.6
34.6.1
34.6.2
34.6.3
34.6.4
34.6.5
34.6.6
34.6.7
34.6.8
34.6.9
Chapter 35: LPC18xx I2S interface
35.1
35.2
35.3
35.4
35.4.1
35.5
35.6
35.6.1
35.6.2
35.6.3
35.6.4
35.6.5
35.6.6
Chapter 36: LPC18xx C_CAN
36.1
36.2
36.3
36.4
36.5
36.6
36.6.1
36.6.1.1
36.6.1.2
36.6.1.3
36.6.1.4
36.6.1.5
36.6.1.6
36.6.1.7
36.6.2
36.6.2.1
36.6.2.2
<Document ID>
User manual
How to read this chapter . . . . . . . . . . . . . . . . 770
Basic configuration . . . . . . . . . . . . . . . . . . . . 770
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
General description . . . . . . . . . . . . . . . . . . . . 770
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 771
Register description . . . . . . . . . . . . . . . . . . . 771
How to read this chapter . . . . . . . . . . . . . . . . 785
Basic configuration . . . . . . . . . . . . . . . . . . . . 785
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
General description . . . . . . . . . . . . . . . . . . . . 786
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 788
Register description . . . . . . . . . . . . . . . . . . . 790
How to read this chapter . . . . . . . . . . . . . . . . 806
Basic configuration . . . . . . . . . . . . . . . . . . . . 806
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
General description . . . . . . . . . . . . . . . . . . . . 807
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 808
Register description . . . . . . . . . . . . . . . . . . . 809
SSPControl Register 0 . . . . . . . . . . . . . . . . 772
SSP Control Register 1 . . . . . . . . . . . . . . . . 773
SSP Data Register . . . . . . . . . . . . . . . . . . . . 774
SSP Status Register . . . . . . . . . . . . . . . . . . 775
SSP Clock Prescale Register . . . . . . . . . . . 775
SSP Interrupt Mask Set/Clear Register . . . . 775
SSP Raw Interrupt Status Register . . . . . . . 776
SSP Masked Interrupt Status Register . . . . 776
SSP Interrupt Clear Register . . . . . . . . . . . . 777
I2S connection schemes . . . . . . . . . . . . . . . 786
I2S Digital Audio Output register . . . . . . . . . 791
I2S Digital Audio Input register . . . . . . . . . . . 792
I2S Transmit FIFO register . . . . . . . . . . . . . 792
Receive FIFO register . . . . . . . . . . . . . . . . . 792
I2S Status Feedback register . . . . . . . . . . . . 793
I2S DMA Configuration Register 1 . . . . . . . . 793
Register values at reset . . . . . . . . . . . . . . . . .809
Timing of read/write operations . . . . . . . . . . .809
CAN protocol registers . . . . . . . . . . . . . . . . . 812
CAN control register . . . . . . . . . . . . . . . . . . . 812
CAN status register . . . . . . . . . . . . . . . . . . . 814
CAN error counter . . . . . . . . . . . . . . . . . . . . 815
CAN bit timing register . . . . . . . . . . . . . . . . . 816
CAN interrupt register . . . . . . . . . . . . . . . . . 816
CAN test register . . . . . . . . . . . . . . . . . . . . . 817
CAN baud rate prescaler extension register 817
Message interface registers . . . . . . . . . . . . . 818
Message objects . . . . . . . . . . . . . . . . . . . . . 819
CAN message interface command request
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
34.6.10
34.7
34.7.1
34.7.2
34.7.2.1
34.7.2.2
34.7.2.3
34.7.2.4
34.7.2.5
34.7.3
34.7.3.1
35.6.7
35.6.8
35.6.9
35.6.9.1
35.6.10
35.6.11
35.6.12
35.6.13
35.6.14
35.7
35.7.1
35.7.2
35.7.3
36.6.2.3
36.6.2.4
36.6.2.4.1 CAN message interface command mask 1
36.6.2.4.2 CAN message interface command mask 2
36.6.2.4.3 CAN message interface command arbitration 1
36.6.2.4.4 CAN message interface command arbitration 2
36.6.2.4.5 CAN message interface message control
36.6.2.4.6 CAN message interface data A1 registers . 832
36.6.2.4.7 CAN message interface data A2 registers. . 833
36.6.2.4.8 CAN message interface data B1 registers . 833
36.6.2.4.9 CAN message interface data B2 registers . 833
36.6.3
36.6.3.1
Functional description . . . . . . . . . . . . . . . . . 778
Functional description . . . . . . . . . . . . . . . . . 798
SSP DMA Control Register . . . . . . . . . . . . . 777
Texas Instruments synchronous serial frame
format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
SPI frame format . . . . . . . . . . . . . . . . . . . . . 779
Clock Polarity (CPOL) and Phase (CPHA) control
779
SPI format with CPOL=0,CPHA=0. . . . . . . . 779
SPI format with CPOL=0,CPHA=1. . . . . . . . 780
SPI format with CPOL = 1,CPHA = 0. . . . . . 781
SPI format with CPOL = 1,CPHA = 1. . . . . . 782
National Semiconductor Microwire frame format .
783
Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 784
I2S DMA Configuration Register 2 . . . . . . . 794
I2S Interrupt Request Control register . . . . . 794
I2S Transmit Clock Rate register . . . . . . . . 795
Notes on fractional rate generators . . . . . . . 795
I2S Receive Clock Rate register . . . . . . . . . 796
I2S Transmit Clock Bit Rate register . . . . . . 796
I2S Receive Clock Bit Rate register . . . . . . 797
I2S Transmit Mode Control register . . . . . . 797
I2S Receive Mode Control register . . . . . . . 797
I
I
FIFO controller . . . . . . . . . . . . . . . . . . . . . . . 804
CAN message interface command mask registers
Transfer direction Write . . . . . . . . . . . . . . . . . 821
Transfer direction Read . . . . . . . . . . . . . . . . . 823
IF1 and IF2 message buffer registers . . . . . 825
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Message handler registers. . . . . . . . . . . . . . 834
CAN transmission request 1 register . . . . . . 834
2
2
821
S transmit and receive interfaces . . . . . . . 798
S operating modes . . . . . . . . . . . . . . . . . . 799
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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