LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1048

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.7.4.3 Pin configuration register for open-drain I
42.7.4.4 EMC clock delay register
Table 967. Pin configuration for pins DP1/DM1 register (SFSUSB, address 0x4008 6C80) bit
Table 968. Pin configuration for open-drain I
This register provides a programmable delay for the EMC clock outputs. The delay for
each clock output is approximately 0.5 ns  CLKn_DELAY or 0.5 ns  CKEn_DELAY.
(CLKn_DELAY/CKEn_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay 
3.5 ns.)
Table 969. EMC clock delay register (EMCCLKDELAY, address 0x4008 6D00) bit description
Bit
1
31:2 -
Bit
0
1
2
31:3
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
Symbol
USB_ESEA
Symbol
SDA_EHS
SCL_EHS
SCL_ECS
-
Symbol
CLK0_DELAY Delay of the EXTBUS_CLK0 clock output.
-
CLK1_DELAY Delay of the EXTBUS_CLK0 clock output.
-
CLK2_DELAY Delay of the EXTBUS_CLK2 clock output.
-
CLK3_DELAY Delay of the EXTBUS_CLK3 clock output.
-
CKE0_DELAY Delay of the EXTBUS_CKEOUT0 clock enable output. 0
-
CKE1_DELAY Delay of the EXTBUS_CKEOUT1 clock enable output. 0
description
6C84) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
Rev. 00.13 — 20 July 2011
Value
0
1
0
1
0
1
Description
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
…continued
Control signal for differential input or single input
Reserved. Do not use.
Single input AIP. Enables USB1.
Reserved
Description
Configures I
Standard/Fast mode (400 kbit/s)
High-speed mode (3.4 Mbit/s)
Configures I
Standard/Fast mode (400 kbit/s)
High-speed mode (3.4 Mbit/s)
Direction (only applies if SCL_EHS = 1)
Receive
Transmit
Reserved
2
2
2
C0-bus speed for SDA0 pin
C0-bus speed for SCL0 pin
C-bus pins register (SFSI2C0, address 0x4008
2
C-bus pins
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
-
Reset
value
0
-
Reset
value
0
-
0
-
0
-
0
-
-
1048 of 1164
Access
-
Access
R/W
R/W
R/W
-
R/W
Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W