LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 898

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

38.1 How to read this chapter
38.2 Basic configuration
38.3 Features
<Document ID>
User manual
The ADC0 and ADC1 are available on all LPC18xx parts.
The following configuration options apply to parts LPC1850_30_20_10 Rev ‘A’ only:
The ADC0 and ADC1 are configured as follows:
Table 825. ADC0/1 clocking and power control
ADC0 clock
ADC1 clock
•
•
•
•
•
•
•
•
•
•
•
•
UM10430
Chapter 38: LPC18xx 10-bit ADC0/1
Rev. 00.13 — 20 July 2011
The ADC start inputs are configured through the GIMA (see
The ADC0 and ADC1 functions are multiplexed with digital functions and need to be
configured using the ENAIO0/1 registers (see
See
The ADC0 is reset by the ADC0_RST (reset # 40).
The ADC1 is reset by the ADC1_RST (reset # 41).
The ADC0 interrupt is connected to interrupt slot # 17 in the NVIC.
The ADC1 interrupt is connected to interrupt slot # 21 in the NVIC.
For connecting to the GPDMA, use the DMAMUX register
block and enable the GPDMA channel in the DMA Channel Configuration registers
Section
External pins (ADCTRIG0/1), the MOTOCON PWM MCOA2 output, and two SCT
outputs can be selected as conversion triggers for ADC0/1 (see
The ADC start inputs are configured through the GIMA (see
The ADC0 and ADC1 functions are multiplexed with digital functions and need to be
configured using the ENAIO0/1 registers (see
10 bit successive approximation analog to digital converter.
Table 825
16.6.20.
Base clock
BASE_APB3_CLK CLK_APB3_ADC0 150 MHz
BASE_APB3_CLK CLK_APB3_ADC1 150 MHz
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Branch clock
Section 13.4.3
Section 13.4.3
Maximum
frequency
(Table
Notes
For register interface and
ADC0 conversion rate.
For register interface and
ADC1 conversion rate.
Section
Section
and
and
Figure
35) in the CREG
Section
Section
© NXP B.V. 2011. All rights reserved.
14.3).
14.3).
User manual
25).
13.4.5.
13.4.5.
898 of 1164