LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1078

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Fig 165. 4-wire receiver master mode sharing the transmitter bit clock and WS
Fig 166. Typical receiver slave mode
Fig 167. Receiver slave mode sharing the transmitter reference clock
Fig 168. 4-wire receiver slave mode sharing the transmitter bit clock and WS
42.9.7.3 FIFO controller
TX_REF
RX_REF
Handling of data for transmission and reception is performed via the FIFO controller which
can generate two DMA requests and an interrupt request. The controller consists of a set
of comparators which compare FIFO levels with depth settings contained in registers. The
current status of the level comparators can be seen in the APB status register.
I2SRXBITRATE[5:0]
I2SRXBITRATE[5:0]
TX bit clock
TX bit clock
(1 to 64)
(1 to 64)
÷N
÷N
All information provided in this document is subject to legal disclaimers.
RX bit clock
RX bit clock
peripheral
(receive)
peripheral
(receive)
Rev. 00.13 — 20 July 2011
block
block
I
I
2
2
S
S
peripheral
(receive)
peripheral
(receive)
block
TX_WS ref
block
TX_WS ref
I
2
I
S
2
S
I2S_RX_SDA
I2S_RX_SCK
I2S_RX_SDA
I2S_RX_SCK
I2S_RX_SDA
I2S_RX_WS
I2S_RX_SDA
I2S_RX_WS
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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