LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 268

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 196. Register overview: GPDMA (base address 0x4000 2000)
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<Document ID>
User manual
Name
Channel 3 registers
C3SRCADDR
C3DESTADDR
C3LLI
C3CONTROL
C3CONFIG
Channel 4 registers
C4SRCADDR
C4DESTADDR
C4LLI
C4CONTROL
C4CONFIG
Channel 5 registers
C5SRCADDR
C5DESTADDR
C5LLI
C5CONTROL
C5CONFIG
Channel 6 registers
C6SRCADDR
C6DESTADDR
C6LLI
C6CONTROL
C6CONFIG
Channel 7 registers
C7SRCADDR
C7DESTADDR
C7LLI
C7CONTROL
C7CONFIG
Bit 17 of this register is a read-only status flag.
16.6.1 DMA Interrupt Status Register
The IntStat Register is read-only and shows the status of the interrupts after masking. A
HIGH bit indicates that a specific DMA channel interrupt request is active. The request
can be generated from either the error or terminal count interrupt requests.
Access Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
offset
0x160
0x164
0x168
0x16C
0x170
0x180
0x184
0x188
0x18C
0x190
0x1A0
0x1A4
0x1A8
0x1AC
0x1B0
0x1C0
0x1C4
0x1C8
01CC
0x1D0
0x1E0
0x1E4
0x1E8
0x1EC
0x1F0
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Description
DMA Channel 3 Source Address Register
DMA Channel 3 Destination Address Register
DMA Channel 3 Linked List Item Register
DMA Channel 3 Control Register
DMA Channel 3 Configuration Register
DMA Channel 4 Source Address Register
DMA Channel 4 Destination Address Register
DMA Channel 4 Linked List Item Register
DMA Channel 4 Control Register
DMA Channel 4 Configuration Register
DMA Channel 5 Source Address Register
DMA Channel 5 Destination Address Register
DMA Channel 5 Linked List Item Register
DMA Channel 5 Control Register
DMA Channel 5 Configuration Register
DMA Channel 6 Source Address Register
DMA Channel 6 Destination Address Register
DMA Channel 6 Linked List Item Register
DMA Channel 6 Control Register
DMA Channel 6 Configuration Register
DMA Channel 7 Source Address Register
DMA Channel 7 Destination Address Register
DMA Channel 7 Linked List Item Register
DMA Channel 7 Control Register
DMA Channel 7 Configuration Register
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
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